| Message ID | 20241123-dts_qcs8300-v4-1-b10b8ac634a9@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/2] arm64: dts: qcom: qcs8300: add the first 2.5G ethernet | expand |
On 2024-11-24 03:36, Andrew Lunn wrote: >> + ethernet0: ethernet@23040000 { >> + compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; >> + reg = <0x0 0x23040000 0x0 0x10000>, >> + <0x0 0x23056000 0x0 0x100>; >> + reg-names = "stmmaceth", "rgmii"; > > Dumb question which should not stop this getting merged. > > Since this is now a MAC using a SERDES, do you still need the rmgii > registers? Can the silicon actually do RGMII? Indeed, the RGMII configuration area is necessary for managing clock settings, even when SERDES is utilized. For instance, the RGMII_CONFIG2_RGMII_CLK_SEL_CFG bit within RGMII_IO_MACRO_CONFIG2 is set in ethqos_configure_sgmii. > > Andrew
On 23.11.2024 9:51 AM, Yijie Yang wrote: > Add the node for the first ethernet interface on qcs8300 platform. > Add the internal SGMII/SerDes PHY node as well. > > Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..718c2756400be884bd28a63c1eac5e8efe1c932d 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@3c40000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + serdes0: phy@8909000 { > + compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; > + reg = <0x0 0x8909000 0x0 0xe10>; Nit: we pad address parts to 8 hex digits with leading zeroes, maybe Bjorn could fix this up while applying otherwise Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..718c2756400be884bd28a63c1eac5e8efe1c932d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + serdes0: phy@8909000 { + compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x8909000 0x0 0xe10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>; @@ -1308,6 +1317,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + ethernet0: ethernet@23040000 { + compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; + reg = <0x0 0x23040000 0x0 0x10000>, + <0x0 0x23056000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + power-domains = <&gcc GCC_EMAC0_GDSC>; + + phys = <&serdes0>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x120 0xf>; + dma-coherent; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + nspa_noc: interconnect@260c0000 { compatible = "qcom,qcs8300-nspa-noc"; reg = <0x0 0x260c0000 0x0 0x16080>;
Add the node for the first ethernet interface on qcs8300 platform. Add the internal SGMII/SerDes PHY node as well. Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)