| Message ID | 20241121-add-mtk-isp-3-0-support-v7-2-b04dc9610619@baylibre.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Mediatek ISP3.0 | expand |
Hi Julien, Thank you for the patch. On Thu, Nov 21, 2024 at 09:53:16AM +0100, Julien Stephan wrote: > From: Phi-bang Nguyen <pnguyen@baylibre.com> > > This adds the bindings, for the ISP3.0 camsv module embedded in > some Mediatek SoC, such as the mt8365 > > Signed-off-by: Phi-bang Nguyen <pnguyen@baylibre.com> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Julien Stephan <jstephan@baylibre.com> > --- > .../bindings/media/mediatek,mt8365-camsv.yaml | 109 +++++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 110 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..fdd07675645917fbcd692606c836efd07e50ac0c > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml > @@ -0,0 +1,109 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2023 MediaTek, BayLibre > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8365-camsv.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek CAMSV 3.0 > + > +maintainers: > + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + - Julien Stephan <jstephan@baylibre.com> > + - Andy Hsieh <andy.hsieh@mediatek.com> > + > +description: > + The CAMSV is a video capture device that includes a DMA engine connected to > + the SENINF CSI-2 receivers. The number of CAMSVs depend on the SoC model. > + > +properties: > + compatible: > + const: mediatek,mt8365-camsv > + > + reg: > + items: > + - description: camsv base > + - description: img0 base > + - description: tg base > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: cam clock > + - description: camtg clock > + - description: camsv clock > + > + clock-names: > + items: > + - const: cam > + - const: camtg > + - const: camsv > + > + iommus: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Connection to the SENINF output > + > + required: > + - port@0 > + > +required: > + - compatible > + - interrupts > + - clocks > + - clock-names > + - power-domains > + - iommus > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mediatek,mt8365-clk.h> I would sort the headers alphabetically. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + #include <dt-bindings/memory/mediatek,mt8365-larb-port.h> > + #include <dt-bindings/power/mediatek,mt8365-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camsv@15050000 { > + compatible = "mediatek,mt8365-camsv"; > + reg = <0 0x15050000 0 0x0040>, > + <0 0x15050208 0 0x0020>, > + <0 0x15050400 0 0x0100>; > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&camsys CLK_CAM>, > + <&camsys CLK_CAMTG>, > + <&camsys CLK_CAMSV0>; > + clock-names = "cam", "camtg", "camsv"; > + iommus = <&iommu M4U_PORT_CAM_IMGO>; > + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + camsv1_endpoint: endpoint { > + remote-endpoint = <&seninf_camsv1_endpoint>; > + }; > + }; > + }; > + }; > + }; > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 242c54c88a4a22fc0cbe5c4fc5d7b0d0f84b329e..6147629405c8d40b00c4755a4ee27a746b26f782 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14570,6 +14570,7 @@ M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > M: Julien Stephan <jstephan@baylibre.com> > M: Andy Hsieh <andy.hsieh@mediatek.com> > S: Supported > +F: Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml > F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml > > MEDIATEK SMI DRIVER
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fdd07675645917fbcd692606c836efd07e50ac0c --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-camsv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek CAMSV 3.0 + +maintainers: + - Laurent Pinchart <laurent.pinchart@ideasonboard.com> + - Julien Stephan <jstephan@baylibre.com> + - Andy Hsieh <andy.hsieh@mediatek.com> + +description: + The CAMSV is a video capture device that includes a DMA engine connected to + the SENINF CSI-2 receivers. The number of CAMSVs depend on the SoC model. + +properties: + compatible: + const: mediatek,mt8365-camsv + + reg: + items: + - description: camsv base + - description: img0 base + - description: tg base + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: cam clock + - description: camtg clock + - description: camsv clock + + clock-names: + items: + - const: cam + - const: camtg + - const: camsv + + iommus: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to the SENINF output + + required: + - port@0 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - iommus + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mediatek,mt8365-clk.h> + #include <dt-bindings/memory/mediatek,mt8365-larb-port.h> + #include <dt-bindings/power/mediatek,mt8365-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camsv@15050000 { + compatible = "mediatek,mt8365-camsv"; + reg = <0 0x15050000 0 0x0040>, + <0 0x15050208 0 0x0020>, + <0 0x15050400 0 0x0100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; + clocks = <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV0>; + clock-names = "cam", "camtg", "camsv"; + iommus = <&iommu M4U_PORT_CAM_IMGO>; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + camsv1_endpoint: endpoint { + remote-endpoint = <&seninf_camsv1_endpoint>; + }; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 242c54c88a4a22fc0cbe5c4fc5d7b0d0f84b329e..6147629405c8d40b00c4755a4ee27a746b26f782 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14570,6 +14570,7 @@ M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> M: Julien Stephan <jstephan@baylibre.com> M: Andy Hsieh <andy.hsieh@mediatek.com> S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml MEDIATEK SMI DRIVER