diff mbox series

[v0,4/6] media: chips-media: wave5: Fix Multistream Decode Hang with no IRQ Present

Message ID 20241112021517.121-5-jackson.lee@chipsnmedia.com
State New
Headers show
Series Improve decoder performance and fix critical bugs | expand

Commit Message

jackson.lee Nov. 12, 2024, 2:15 a.m. UTC 
In multistream decode case when polling is used, a hang can occur in two
different locations. Firstly, the work function that is called every 5ms to
service any possible interrupts triggered by the VPU. While handling VPU
IRQ, there is corner case where another decoded picture IRQ event could
occur. Before marking command as handled on the VPU, make sure that another
decoded picture IRQ event hasn't occurred so the event isn't lost.

Secondly, during stop_streaming, there is a check in place to see if any
decoded pictures remain. If there are, a call is made to wait for the
interrupt to trigger in order to service the decoded picture. However, this
interrupt won't be seen since polling is being used. A timeout will then
occur after one minute. Remove this wait and allow work handler to keep
running until last picture is serviced.

Signed-off-by: Jackson.lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
---
 .../media/platform/chips-media/wave5/wave5-vpu.c   | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c
index a9bd96cbf9ac..9bc216052a15 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c
@@ -51,6 +51,7 @@  static void wave5_vpu_handle_irq(void *dev_id)
 	u32 seq_done;
 	u32 cmd_done;
 	u32 irq_reason;
+	u32 irq_subreason;
 	struct vpu_instance *inst, *tmp;
 	struct vpu_device *dev = dev_id;
 
@@ -81,8 +82,17 @@  static void wave5_vpu_handle_irq(void *dev_id)
 		    irq_reason & BIT(INT_WAVE5_ENC_PIC)) {
 			if (cmd_done & BIT(inst->id)) {
 				cmd_done &= ~BIT(inst->id);
-				wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,
-							 cmd_done);
+				if (dev->irq < 0) {
+					irq_subreason =
+						wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
+					if (!(irq_subreason & BIT(INT_WAVE5_DEC_PIC)))
+						wave5_vdi_write_register(dev,
+									 W5_RET_QUEUE_CMD_DONE_INST,
+									 cmd_done);
+				} else {
+					wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,
+								 cmd_done);
+				}
 				inst->ops->finish_process(inst);
 			}
 		}