diff mbox series

[v2,50/54] target/xtensa: Convert to TCGCPUOps.tlb_fill_align

Message ID 20241114160131.48616-51-richard.henderson@linaro.org
State New
Headers show
Series accel/tcg: Convert victim tlb to IntervalTree | expand

Commit Message

Richard Henderson Nov. 14, 2024, 4:01 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/cpu.h    |  8 +++++---
 target/xtensa/cpu.c    |  2 +-
 target/xtensa/helper.c | 28 ++++++++++++++++++++--------
 3 files changed, 26 insertions(+), 12 deletions(-)

Comments

Pierrick Bouvier Nov. 14, 2024, 6:54 p.m. UTC | #1 
On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/xtensa/cpu.h    |  8 +++++---
>   target/xtensa/cpu.c    |  2 +-
>   target/xtensa/helper.c | 28 ++++++++++++++++++++--------
>   3 files changed, 26 insertions(+), 12 deletions(-)
> 
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 77e48eef19..68c3d90d41 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -31,6 +31,7 @@
>   #include "cpu-qom.h"
>   #include "qemu/cpu-float.h"
>   #include "exec/cpu-defs.h"
> +#include "exec/memop.h"
>   #include "hw/clock.h"
>   #include "xtensa-isa.h"
>   
> @@ -580,9 +581,10 @@ struct XtensaCPUClass {
>   };
>   
>   #ifndef CONFIG_USER_ONLY
> -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                         MMUAccessType access_type, int mmu_idx,
> -                         bool probe, uintptr_t retaddr);
> +bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> +                               vaddr addr, MMUAccessType access_type,
> +                               int mmu_idx, MemOp memop, int size,
> +                               bool probe, uintptr_t retaddr);
>   void xtensa_cpu_do_interrupt(CPUState *cpu);
>   bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
>   void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index 6f9039abae..3e4ec97e0e 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -232,7 +232,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
>       .restore_state_to_opc = xtensa_restore_state_to_opc,
>   
>   #ifndef CONFIG_USER_ONLY
> -    .tlb_fill = xtensa_cpu_tlb_fill,
> +    .tlb_fill_align = xtensa_cpu_tlb_fill_align,
>       .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
>       .cpu_exec_halt = xtensa_cpu_has_work,
>       .do_interrupt = xtensa_cpu_do_interrupt,
> diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
> index ca214b948a..69b0e661c8 100644
> --- a/target/xtensa/helper.c
> +++ b/target/xtensa/helper.c
> @@ -261,15 +261,26 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs,
>                                     addr);
>   }
>   
> -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                         MMUAccessType access_type, int mmu_idx,
> -                         bool probe, uintptr_t retaddr)
> +bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> +                               vaddr address, MMUAccessType access_type,
> +                               int mmu_idx, MemOp memop, int size,
> +                               bool probe, uintptr_t retaddr)
>   {
>       CPUXtensaState *env = cpu_env(cs);
>       uint32_t paddr;
>       uint32_t page_size;
>       unsigned access;
> -    int ret = xtensa_get_physical_addr(env, true, address, access_type,
> +    int ret;
> +
> +    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
> +        if (probe) {
> +            return false;
> +        }
> +        xtensa_cpu_do_unaligned_access(cs, address, access_type,
> +                                       mmu_idx, retaddr);
> +    }
> +
> +    ret = xtensa_get_physical_addr(env, true, address, access_type,
>                                          mmu_idx, &paddr, &page_size, &access);
>   
>       qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx
> @@ -277,10 +288,11 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>                     __func__, address, access_type, mmu_idx, paddr, ret);
>   
>       if (ret == 0) {
> -        tlb_set_page(cs,
> -                     address & TARGET_PAGE_MASK,
> -                     paddr & TARGET_PAGE_MASK,
> -                     access, mmu_idx, page_size);
> +        memset(out, 0, sizeof(*out));
> +        out->phys_addr = paddr;
> +        out->prot = access;
> +        out->lg_page_size = ctz32(page_size);
> +        out->attrs = MEMTXATTRS_UNSPECIFIED;
>           return true;
>       } else if (probe) {
>           return false;

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 77e48eef19..68c3d90d41 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,7 @@ 
 #include "cpu-qom.h"
 #include "qemu/cpu-float.h"
 #include "exec/cpu-defs.h"
+#include "exec/memop.h"
 #include "hw/clock.h"
 #include "xtensa-isa.h"
 
@@ -580,9 +581,10 @@  struct XtensaCPUClass {
 };
 
 #ifndef CONFIG_USER_ONLY
-bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                         MMUAccessType access_type, int mmu_idx,
-                         bool probe, uintptr_t retaddr);
+bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
+                               vaddr addr, MMUAccessType access_type,
+                               int mmu_idx, MemOp memop, int size,
+                               bool probe, uintptr_t retaddr);
 void xtensa_cpu_do_interrupt(CPUState *cpu);
 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 6f9039abae..3e4ec97e0e 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -232,7 +232,7 @@  static const TCGCPUOps xtensa_tcg_ops = {
     .restore_state_to_opc = xtensa_restore_state_to_opc,
 
 #ifndef CONFIG_USER_ONLY
-    .tlb_fill = xtensa_cpu_tlb_fill,
+    .tlb_fill_align = xtensa_cpu_tlb_fill_align,
     .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
     .cpu_exec_halt = xtensa_cpu_has_work,
     .do_interrupt = xtensa_cpu_do_interrupt,
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index ca214b948a..69b0e661c8 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -261,15 +261,26 @@  void xtensa_cpu_do_unaligned_access(CPUState *cs,
                                   addr);
 }
 
-bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                         MMUAccessType access_type, int mmu_idx,
-                         bool probe, uintptr_t retaddr)
+bool xtensa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
+                               vaddr address, MMUAccessType access_type,
+                               int mmu_idx, MemOp memop, int size,
+                               bool probe, uintptr_t retaddr)
 {
     CPUXtensaState *env = cpu_env(cs);
     uint32_t paddr;
     uint32_t page_size;
     unsigned access;
-    int ret = xtensa_get_physical_addr(env, true, address, access_type,
+    int ret;
+
+    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
+        if (probe) {
+            return false;
+        }
+        xtensa_cpu_do_unaligned_access(cs, address, access_type,
+                                       mmu_idx, retaddr);
+    }
+
+    ret = xtensa_get_physical_addr(env, true, address, access_type,
                                        mmu_idx, &paddr, &page_size, &access);
 
     qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx
@@ -277,10 +288,11 @@  bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                   __func__, address, access_type, mmu_idx, paddr, ret);
 
     if (ret == 0) {
-        tlb_set_page(cs,
-                     address & TARGET_PAGE_MASK,
-                     paddr & TARGET_PAGE_MASK,
-                     access, mmu_idx, page_size);
+        memset(out, 0, sizeof(*out));
+        out->phys_addr = paddr;
+        out->prot = access;
+        out->lg_page_size = ctz32(page_size);
+        out->attrs = MEMTXATTRS_UNSPECIFIED;
         return true;
     } else if (probe) {
         return false;