diff mbox series

[v2,34/54] target/alpha: Convert to TCGCPUOps.tlb_fill_align

Message ID 20241114160131.48616-35-richard.henderson@linaro.org
State New
Headers show
Series accel/tcg: Convert victim tlb to IntervalTree | expand

Commit Message

Richard Henderson Nov. 14, 2024, 4:01 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/cpu.h    |  6 +++---
 target/alpha/cpu.c    |  2 +-
 target/alpha/helper.c | 23 +++++++++++++++++------
 3 files changed, 21 insertions(+), 10 deletions(-)

Comments

Pierrick Bouvier Nov. 14, 2024, 6:53 p.m. UTC | #1 
On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/alpha/cpu.h    |  6 +++---
>   target/alpha/cpu.c    |  2 +-
>   target/alpha/helper.c | 23 +++++++++++++++++------
>   3 files changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index 3556d3227f..70331c0b83 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -449,9 +449,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
>   void alpha_cpu_record_sigbus(CPUState *cs, vaddr address,
>                                MMUAccessType access_type, uintptr_t retaddr);
>   #else
> -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                        MMUAccessType access_type, int mmu_idx,
> -                        bool probe, uintptr_t retaddr);
> +bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
> +                              MMUAccessType access_type, int mmu_idx,
> +                              MemOp memop, int size, bool probe, uintptr_t ra);
>   G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
>                                                 MMUAccessType access_type, int mmu_idx,
>                                                 uintptr_t retaddr);
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index 5d75c941f7..7bcc48420d 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -228,7 +228,7 @@ static const TCGCPUOps alpha_tcg_ops = {
>       .record_sigsegv = alpha_cpu_record_sigsegv,
>       .record_sigbus = alpha_cpu_record_sigbus,
>   #else
> -    .tlb_fill = alpha_cpu_tlb_fill,
> +    .tlb_fill_align = alpha_cpu_tlb_fill_align,
>       .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
>       .cpu_exec_halt = alpha_cpu_has_work,
>       .do_interrupt = alpha_cpu_do_interrupt,
> diff --git a/target/alpha/helper.c b/target/alpha/helper.c
> index 2f1000c99f..26eadfe3ca 100644
> --- a/target/alpha/helper.c
> +++ b/target/alpha/helper.c
> @@ -294,14 +294,21 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>       return (fail >= 0 ? -1 : phys);
>   }
>   
> -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
> -                        MMUAccessType access_type, int mmu_idx,
> -                        bool probe, uintptr_t retaddr)
> +bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
> +                              MMUAccessType access_type, int mmu_idx,
> +                              MemOp memop, int size, bool probe, uintptr_t ra)
>   {
>       CPUAlphaState *env = cpu_env(cs);
>       target_ulong phys;
>       int prot, fail;
>   
> +    if (addr & ((1 << memop_alignment_bits(memop)) - 1)) {
> +        if (probe) {
> +            return false;
> +        }
> +        alpha_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, ra);
> +    }
> +
>       fail = get_physical_address(env, addr, 1 << access_type,
>                                   mmu_idx, &phys, &prot);
>       if (unlikely(fail >= 0)) {
> @@ -314,11 +321,15 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
>           env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull :
>                             access_type == MMU_DATA_STORE ? 1ull :
>                             /* access_type == MMU_INST_FETCH */ -1ull);
> -        cpu_loop_exit_restore(cs, retaddr);
> +        cpu_loop_exit_restore(cs, ra);
>       }
>   
> -    tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
> -                 prot, mmu_idx, TARGET_PAGE_SIZE);
> +    memset(out, 0, sizeof(*out));
> +    out->phys_addr = phys;
> +    out->prot = prot;
> +    out->attrs = MEMTXATTRS_UNSPECIFIED;
> +    out->lg_page_size = TARGET_PAGE_BITS;
> +
>       return true;
>   }
>   

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 3556d3227f..70331c0b83 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -449,9 +449,9 @@  void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
 void alpha_cpu_record_sigbus(CPUState *cs, vaddr address,
                              MMUAccessType access_type, uintptr_t retaddr);
 #else
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                        MMUAccessType access_type, int mmu_idx,
-                        bool probe, uintptr_t retaddr);
+bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
+                              MMUAccessType access_type, int mmu_idx,
+                              MemOp memop, int size, bool probe, uintptr_t ra);
 G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                               MMUAccessType access_type, int mmu_idx,
                                               uintptr_t retaddr);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 5d75c941f7..7bcc48420d 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -228,7 +228,7 @@  static const TCGCPUOps alpha_tcg_ops = {
     .record_sigsegv = alpha_cpu_record_sigsegv,
     .record_sigbus = alpha_cpu_record_sigbus,
 #else
-    .tlb_fill = alpha_cpu_tlb_fill,
+    .tlb_fill_align = alpha_cpu_tlb_fill_align,
     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
     .cpu_exec_halt = alpha_cpu_has_work,
     .do_interrupt = alpha_cpu_do_interrupt,
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 2f1000c99f..26eadfe3ca 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -294,14 +294,21 @@  hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     return (fail >= 0 ? -1 : phys);
 }
 
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
-                        MMUAccessType access_type, int mmu_idx,
-                        bool probe, uintptr_t retaddr)
+bool alpha_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
+                              MMUAccessType access_type, int mmu_idx,
+                              MemOp memop, int size, bool probe, uintptr_t ra)
 {
     CPUAlphaState *env = cpu_env(cs);
     target_ulong phys;
     int prot, fail;
 
+    if (addr & ((1 << memop_alignment_bits(memop)) - 1)) {
+        if (probe) {
+            return false;
+        }
+        alpha_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, ra);
+    }
+
     fail = get_physical_address(env, addr, 1 << access_type,
                                 mmu_idx, &phys, &prot);
     if (unlikely(fail >= 0)) {
@@ -314,11 +321,15 @@  bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
         env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull :
                           access_type == MMU_DATA_STORE ? 1ull :
                           /* access_type == MMU_INST_FETCH */ -1ull);
-        cpu_loop_exit_restore(cs, retaddr);
+        cpu_loop_exit_restore(cs, ra);
     }
 
-    tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
-                 prot, mmu_idx, TARGET_PAGE_SIZE);
+    memset(out, 0, sizeof(*out));
+    out->phys_addr = phys;
+    out->prot = prot;
+    out->attrs = MEMTXATTRS_UNSPECIFIED;
+    out->lg_page_size = TARGET_PAGE_BITS;
+
     return true;
 }