diff mbox series

[v2,36/54] target/i386: Convert to TCGCPUOps.tlb_fill_align

Message ID 20241114160131.48616-37-richard.henderson@linaro.org
State New
Headers show
Series accel/tcg: Convert victim tlb to IntervalTree | expand

Commit Message

Richard Henderson Nov. 14, 2024, 4:01 p.m. UTC
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/tcg/helper-tcg.h         |  6 +++---
 target/i386/tcg/sysemu/excp_helper.c | 28 ++++++++++++++++------------
 target/i386/tcg/tcg-cpu.c            |  2 +-
 3 files changed, 20 insertions(+), 16 deletions(-)

Comments

Pierrick Bouvier Nov. 14, 2024, 6:53 p.m. UTC | #1
On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/i386/tcg/helper-tcg.h         |  6 +++---
>   target/i386/tcg/sysemu/excp_helper.c | 28 ++++++++++++++++------------
>   target/i386/tcg/tcg-cpu.c            |  2 +-
>   3 files changed, 20 insertions(+), 16 deletions(-)
> 
> diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
> index 696d6ef016..b2164f41e6 100644
> --- a/target/i386/tcg/helper-tcg.h
> +++ b/target/i386/tcg/helper-tcg.h
> @@ -79,9 +79,9 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
>   void x86_cpu_record_sigbus(CPUState *cs, vaddr addr,
>                              MMUAccessType access_type, uintptr_t ra);
>   #else
> -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                      MMUAccessType access_type, int mmu_idx,
> -                      bool probe, uintptr_t retaddr);
> +bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
> +                            MMUAccessType access_type, int mmu_idx,
> +                            MemOp memop, int size, bool probe, uintptr_t ra);
>   G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>                                               MMUAccessType access_type,
>                                               int mmu_idx, uintptr_t retaddr);
> diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
> index 168ff8e5f3..d23d28fef5 100644
> --- a/target/i386/tcg/sysemu/excp_helper.c
> +++ b/target/i386/tcg/sysemu/excp_helper.c
> @@ -601,25 +601,29 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,
>       return true;
>   }
>   
> -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
> -                      MMUAccessType access_type, int mmu_idx,
> -                      bool probe, uintptr_t retaddr)
> +bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *full, vaddr addr,
> +                            MMUAccessType access_type, int mmu_idx,
> +                            MemOp memop, int size, bool probe,
> +                            uintptr_t retaddr)
>   {
>       CPUX86State *env = cpu_env(cs);
>       TranslateResult out;
>       TranslateFault err;
>   
> +    if (addr & ((1 << memop_alignment_bits(memop)) - 1)) {
> +        if (probe) {
> +            return false;
> +        }
> +        x86_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, retaddr);
> +    }
> +
>       if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err,
>                                retaddr)) {
> -        /*
> -         * Even if 4MB pages, we map only one 4KB page in the cache to
> -         * avoid filling it too fast.
> -         */
> -        assert(out.prot & (1 << access_type));
> -        tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,
> -                                out.paddr & TARGET_PAGE_MASK,
> -                                cpu_get_mem_attrs(env),
> -                                out.prot, mmu_idx, out.page_size);
> +        memset(full, 0, sizeof(*full));
> +        full->phys_addr = out.paddr;
> +        full->prot = out.prot;
> +        full->lg_page_size = ctz32(out.page_size);
> +        full->attrs = cpu_get_mem_attrs(env);
>           return true;
>       }
>   
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index cca19cd40e..6fce6227c7 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -117,7 +117,7 @@ static const TCGCPUOps x86_tcg_ops = {
>       .record_sigsegv = x86_cpu_record_sigsegv,
>       .record_sigbus = x86_cpu_record_sigbus,
>   #else
> -    .tlb_fill = x86_cpu_tlb_fill,
> +    .tlb_fill_align = x86_cpu_tlb_fill_align,
>       .do_interrupt = x86_cpu_do_interrupt,
>       .cpu_exec_halt = x86_cpu_exec_halt,
>       .cpu_exec_interrupt = x86_cpu_exec_interrupt,

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index 696d6ef016..b2164f41e6 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -79,9 +79,9 @@  void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
 void x86_cpu_record_sigbus(CPUState *cs, vaddr addr,
                            MMUAccessType access_type, uintptr_t ra);
 #else
-bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                      MMUAccessType access_type, int mmu_idx,
-                      bool probe, uintptr_t retaddr);
+bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
+                            MMUAccessType access_type, int mmu_idx,
+                            MemOp memop, int size, bool probe, uintptr_t ra);
 G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
                                             MMUAccessType access_type,
                                             int mmu_idx, uintptr_t retaddr);
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 168ff8e5f3..d23d28fef5 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -601,25 +601,29 @@  static bool get_physical_address(CPUX86State *env, vaddr addr,
     return true;
 }
 
-bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
-                      MMUAccessType access_type, int mmu_idx,
-                      bool probe, uintptr_t retaddr)
+bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *full, vaddr addr,
+                            MMUAccessType access_type, int mmu_idx,
+                            MemOp memop, int size, bool probe,
+                            uintptr_t retaddr)
 {
     CPUX86State *env = cpu_env(cs);
     TranslateResult out;
     TranslateFault err;
 
+    if (addr & ((1 << memop_alignment_bits(memop)) - 1)) {
+        if (probe) {
+            return false;
+        }
+        x86_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, retaddr);
+    }
+
     if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err,
                              retaddr)) {
-        /*
-         * Even if 4MB pages, we map only one 4KB page in the cache to
-         * avoid filling it too fast.
-         */
-        assert(out.prot & (1 << access_type));
-        tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,
-                                out.paddr & TARGET_PAGE_MASK,
-                                cpu_get_mem_attrs(env),
-                                out.prot, mmu_idx, out.page_size);
+        memset(full, 0, sizeof(*full));
+        full->phys_addr = out.paddr;
+        full->prot = out.prot;
+        full->lg_page_size = ctz32(out.page_size);
+        full->attrs = cpu_get_mem_attrs(env);
         return true;
     }
 
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index cca19cd40e..6fce6227c7 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -117,7 +117,7 @@  static const TCGCPUOps x86_tcg_ops = {
     .record_sigsegv = x86_cpu_record_sigsegv,
     .record_sigbus = x86_cpu_record_sigbus,
 #else
-    .tlb_fill = x86_cpu_tlb_fill,
+    .tlb_fill_align = x86_cpu_tlb_fill_align,
     .do_interrupt = x86_cpu_do_interrupt,
     .cpu_exec_halt = x86_cpu_exec_halt,
     .cpu_exec_interrupt = x86_cpu_exec_interrupt,