@@ -7,7 +7,7 @@
/dts-v1/;
-#include "ipq6018.dtsi"
+#include "ipq6018-mp5496.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
new file mode 100644
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that
+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC.
+ */
+
+#include "ipq6018.dtsi"
+
+&cpu0 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu1 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu2 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu3 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+};
@@ -43,7 +43,6 @@ cpu0: cpu@0 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -56,7 +55,6 @@ cpu1: cpu@1 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -69,7 +67,6 @@ cpu2: cpu@2 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -82,7 +79,6 @@ cpu3: cpu@3 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -184,16 +180,6 @@ glink-edge {
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm";
qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
};
};
};
Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 -------- 3 files changed, 36 insertions(+), 15 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi