Message ID | 20241108-qcs615-mm-clockcontroller-v3-11-7d3b2d235fdf@quicinc.com |
---|---|
State | New |
Headers | show
Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CFDC1946DF; Fri, 8 Nov 2024 04:11:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039070; cv=none; b=ut6NlleBvn0DZ0tbFicO/8/RNCXiaGeE4ynlz8DLi64waV8eaH7TCKzb85CzjkIJjzE579HrTsVtL2mWZk2dd75tZfkVMKjzQEgg5Zqsrjc03d/fbVC39JAHeHFIUcfyQiGT4aqvqY5rggTW4NHkdizw68Fs8fOqWD9qVgG4zss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039070; c=relaxed/simple; bh=LB0ERSXQL/Llu9CsxiUVYqiS/OzFA+1sg2d30cc2eNI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cgIBVvpIPj9L2xMkOwOGt7On3cgdE8NzZgwp7ZLo0XPyphayAJBMAs7Qlbqlp3IXGamlvZEsLT9TMn+hH4ClcjBNrmQJn1/r6AItMPqrIFndRKqMduiOfbhOPzVsZFa8+CopGijTnNDjFTJzYTsLOprO2lWL1kzByc8knRXSUq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=HWzlD2nz; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HWzlD2nz" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Mb2bV030659; Fri, 8 Nov 2024 04:10:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= t1cA9NDwFLH5+vfmPGgF5z/CRZpfWRBSGlRVBz5PXQE=; b=HWzlD2nzjTsPUkYW 4GZDqH7hqdwse2TbOtJ78C+VGiDXfdXwfJahU/OurYTWsa4GKY/F13nIwaFcrJfE L1YzmndH8h/jUSn5DRr5k3n3fqeWv9JRozSbMLwv375TSkxau56XP5M+T5EQp2Io z5tkGc9TB2dqgn6eS1uN0kwwmUSrtH7ba1y/Ox37nFl75YP3ao/CWFtXeazQf3hq nQZjH3KKntd/36HxyPAGw8fTIj+ef7ZomwS/tcmPG8CvDEb5p0bVxynuZzP0+w6q ZyDK4ICaUG6P5WtQcPkV5GSU775A/h6wMmidwjcqQJWEMNlSrVLGIMzyIodV3UDm Av52NA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gdrkpu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Nov 2024 04:10:40 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A84AdI1017790 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Nov 2024 04:10:39 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 20:10:34 -0800 From: Taniya Das <quic_tdas@quicinc.com> Date: Fri, 8 Nov 2024 09:39:28 +0530 Subject: [PATCH v3 11/11] arm64: defconfig: Enable QCS615 clock controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20241108-qcs615-mm-clockcontroller-v3-11-7d3b2d235fdf@quicinc.com> References: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> In-Reply-To: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> To: Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Abhishek Sahu <absahu@codeaurora.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org> CC: Ajit Pandey <quic_ajipan@quicinc.com>, Imran Shaik <quic_imrashai@quicinc.com>, Jagadeesh Kona <quic_jkona@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Taniya Das <quic_tdas@quicinc.com> X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: lzLao80oBNAttmrh5-Ggi8TzDY48jHFT X-Proofpoint-ORIG-GUID: lzLao80oBNAttmrh5-Ggi8TzDY48jHFT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 mlxlogscore=693 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411080034 |
Series |
Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform
|
expand
|
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 730f303350c36a75661dc267fdd0f8f3088153fc..2fa666156b88b44a8298651e276c196cded9a7f8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1322,7 +1322,11 @@ CONFIG_MSM_GCC_8998=y CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m +CONFIG_QCS_DISPCC_615=m +CONFIG_QCS_CAMCC_615=m CONFIG_QCS_GCC_404=y +CONFIG_QCS_GPUCC_615=m +CONFIG_QCS_VIDEOCC_615=m CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m
Enable the QCS615 display, video, camera and graphics clock controller for their respective functionalities on the Qualcomm QCS615 ride platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+)