@@ -137,6 +137,93 @@ soc@0 {
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
+ efuse@a4000 {
+ compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
+ reg = <0 0x000a4000 0 0x741>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ s9: s9@3dc {
+ reg = <0x3dc 0x1>;
+ bits = <4 4>;
+ };
+
+ s10: s10@3dd {
+ reg = <0x3dd 0x1>;
+ bits = <0 4>;
+ };
+
+ s11: s11@3dd {
+ reg = <0x3dd 0x1>;
+ bits = <4 4>;
+ };
+
+ s12: s12@3de {
+ reg = <0x3de 0x1>;
+ bits = <0 4>;
+ };
+
+ s13: s13@3de {
+ reg = <0x3de 0x1>;
+ bits = <4 4>;
+ };
+
+ s14: s14@3e5 {
+ reg = <0x3e5 0x2>;
+ bits = <7 4>;
+ };
+
+ s15: s15@3e6 {
+ reg = <0x3e6 0x1>;
+ bits = <3 4>;
+ };
+
+ tsens_mode: mode@419 {
+ reg = <0x419 0x1>;
+ bits = <0 3>;
+ };
+
+ tsens_base0: base0@419 {
+ reg = <0x419 0x2>;
+ bits = <3 10>;
+ };
+
+ tsens_base1: base1@41a {
+ reg = <0x41a 0x2>;
+ bits = <5 10>;
+ };
+ };
+
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq5424-tsens";
+ reg = <0 0x004a9000 0 0x1000>,
+ <0 0x004a8000 0 0x1000>;
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base0>,
+ <&tsens_base1>,
+ <&s9>,
+ <&s10>,
+ <&s11>,
+ <&s12>,
+ <&s13>,
+ <&s14>,
+ <&s15>;
+ nvmem-cell-names = "mode",
+ "base0",
+ "base1",
+ "s9",
+ "s10",
+ "s11",
+ "s12",
+ "s13",
+ "s14",
+ "s15";
+ interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "combined";
+ #qcom,sensors = <7>;
+ #thermal-sensor-cells = <1>;
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
IPQ5424 has tsens v2.3.3 peripheral. This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- Changes in V7: - No change arch/arm64/boot/dts/qcom/ipq5424.dtsi | 87 +++++++++++++++++++++++++++ 1 file changed, 87 insertions(+)