| Message ID | 20241023174357.34338-5-mario.limonciello@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
On Wed, Oct 23, 2024 at 12:43:56PM -0500, Mario Limonciello wrote: > From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> > > Sometimes it is required to take actions based on if a CPU is a performance > or efficiency core. As an example, intel_pstate driver uses the Intel > core-type to determine CPU scaling. Also, some CPU vulnerabilities only > affect a specific CPU type, like RFDS only affects Intel Atom. Hybrid > systems that have variants P+E, P-only(Core) and E-only(Atom), it is not > straightforward to identify which variant is affected by a type specific > vulnerability. > > Such processors do have CPUID field that can uniquely identify them. Like, > P+E, P-only and E-only enumerates CPUID.1A.CORE_TYPE identification, while > P+E additionally enumerates CPUID.7.HYBRID. Based on this information, it > is possible for boot CPU to identify if a system has mixed CPU types. > > Add a new field hw_cpu_type to struct cpuinfo_topology that stores the > hardware specific CPU type. This saves the overhead of IPIs to get the CPU > type of a different CPU. CPU type is populated early in the boot process, > before vulnerabilities are enumerated. > > Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> > Co-developed-by: Mario Limonciello <mario.limonciello@amd.com> > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > --- > v2->v3: > * Remove a bunch of boilerplate code > * Convert to showing string in debugfs > * Rename to get_topology_generic_cpu_type/get_topology_cpu_type_name > * Add Intel definitions to intel-family.h > --- > arch/x86/include/asm/intel-family.h | 6 +++++ > arch/x86/include/asm/processor.h | 18 ++++++++++++++ > arch/x86/include/asm/topology.h | 9 +++++++ > arch/x86/kernel/cpu/debugfs.c | 1 + > arch/x86/kernel/cpu/topology_amd.c | 3 +++ > arch/x86/kernel/cpu/topology_common.c | 34 +++++++++++++++++++++++++++ > 6 files changed, 71 insertions(+) Except the minor touchup below, I don't have any complaints about this anymore. Intel folks? diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 795619ea1334..9f9376db64e3 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -156,7 +156,7 @@ extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); -enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c); +enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c); static inline unsigned int topology_max_packages(void) { diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 60d5d74189a3..8277c64f88db 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -28,7 +28,7 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, } } -enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c) +enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c) { if (c->x86_vendor == X86_VENDOR_INTEL) { switch (c->topo.intel_type) { @@ -48,7 +48,7 @@ enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c) const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) { - switch (get_topology_generic_cpu_type(c)) { + switch (get_topology_cpu_type(c)) { case TOPO_CPU_TYPE_PERFORMANCE: return "performance"; case TOPO_CPU_TYPE_EFFICIENCY:
On 10/25/24 06:47, Borislav Petkov wrote: > Except the minor touchup below, I don't have any complaints about this > anymore. > > Intel folks? Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 1a42f829667a3..7367644720484 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -183,4 +183,10 @@ /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ +/* CPU core types */ +enum intel_cpu_type { + INTEL_CPU_TYPE_ATOM = 0x20, + INTEL_CPU_TYPE_CORE = 0x40, +}; + #endif /* _ASM_X86_INTEL_FAMILY_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4a686f0e5dbf6..c0975815980c8 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -105,6 +105,24 @@ struct cpuinfo_topology { // Cache level topology IDs u32 llc_id; u32 l2c_id; + + // Hardware defined CPU-type + union { + u32 cpu_type; + struct { + // CPUID.1A.EAX[23-0] + u32 intel_native_model_id :24; + // CPUID.1A.EAX[31-24] + u32 intel_type :8; + }; + struct { + // CPUID 0x80000026.EBX + u32 amd_num_processors :16, + amd_power_eff_ranking :8, + amd_native_model_id :4, + amd_type :4; + }; + }; }; struct cpuinfo_x86 { diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index aef70336d6247..795619ea13346 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -114,6 +114,12 @@ enum x86_topology_domains { TOPO_MAX_DOMAIN, }; +enum x86_topology_cpu_type { + TOPO_CPU_TYPE_PERFORMANCE, + TOPO_CPU_TYPE_EFFICIENCY, + TOPO_CPU_TYPE_UNKNOWN, +}; + struct x86_topology_system { unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_size[TOPO_MAX_DOMAIN]; @@ -149,6 +155,9 @@ extern unsigned int __max_threads_per_core; extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); +enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c); + static inline unsigned int topology_max_packages(void) { return __max_logical_packages; diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e4358347..10719aba62768 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -22,6 +22,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "cpu_type: %s\n", get_topology_cpu_type_name(c)); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c index 7d476fa697ca5..03b3c9c3a45e2 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -182,6 +182,9 @@ static void parse_topology_amd(struct topo_scan *tscan) if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) has_topoext = cpu_parse_topology_ext(tscan); + if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); + if (!has_topoext && !parse_8000_0008(tscan)) return; diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 9a6069e7133c9..60d5d74189a30 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -3,6 +3,7 @@ #include <xen/xen.h> +#include <asm/intel-family.h> #include <asm/apic.h> #include <asm/processor.h> #include <asm/smp.h> @@ -27,6 +28,36 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, } } +enum x86_topology_cpu_type get_topology_generic_cpu_type(struct cpuinfo_x86 *c) +{ + if (c->x86_vendor == X86_VENDOR_INTEL) { + switch (c->topo.intel_type) { + case INTEL_CPU_TYPE_ATOM: return TOPO_CPU_TYPE_EFFICIENCY; + case INTEL_CPU_TYPE_CORE: return TOPO_CPU_TYPE_PERFORMANCE; + } + } + if (c->x86_vendor == X86_VENDOR_AMD) { + switch (c->topo.amd_type) { + case 0: return TOPO_CPU_TYPE_PERFORMANCE; + case 1: return TOPO_CPU_TYPE_EFFICIENCY; + } + } + + return TOPO_CPU_TYPE_UNKNOWN; +} + +const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) +{ + switch (get_topology_generic_cpu_type(c)) { + case TOPO_CPU_TYPE_PERFORMANCE: + return "performance"; + case TOPO_CPU_TYPE_EFFICIENCY: + return "efficiency"; + default: + return "unknown"; + } +} + static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { @@ -87,6 +118,7 @@ static void parse_topology(struct topo_scan *tscan, bool early) .cu_id = 0xff, .llc_id = BAD_APICID, .l2c_id = BAD_APICID, + .cpu_type = TOPO_CPU_TYPE_UNKNOWN, }; struct cpuinfo_x86 *c = tscan->c; struct { @@ -132,6 +164,8 @@ static void parse_topology(struct topo_scan *tscan, bool early) case X86_VENDOR_INTEL: if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); + if (c->cpuid_level >= 0x1a) + c->topo.cpu_type = cpuid_eax(0x1a); break; case X86_VENDOR_HYGON: if (IS_ENABLED(CONFIG_CPU_SUP_HYGON))