| Message ID | 20241017-sar2130p-clocks-v1-13-f75e740f0a8d@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: add support for clock controllers on the SAR2130P platform | expand |
On 17/10/2024 18:57, Dmitry Baryshkov wrote: > The display clock controller on SAR2130P is very close to the clock > controller on SM8550 (and SM8650). Reuse existing driver to add support > for the controller on SAR2130P. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/Kconfig | 4 ++-- > drivers/clk/qcom/dispcc-sm8550.c | 18 ++++++++++++++++-- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d..f314f26fe136c0fc1612edc0cca23c4deba5cd9f 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -968,10 +968,10 @@ config SM_DISPCC_8450 > config SM_DISPCC_8550 > tristate "SM8550 Display Clock Controller" > depends on ARM64 || COMPILE_TEST > - depends on SM_GCC_8550 || SM_GCC_8650 > + depends on SM_GCC_8550 || SM_GCC_8650 || SAR_GCC_2130P > help > Support for the display clock controller on Qualcomm Technologies, Inc > - SM8550 or SM8650 devices. > + SAR2130P, SM8550 or SM8650 devices. > Say Y if you want to support display devices and functionality such as > splash screen. > > diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c > index 7f9021ca0ecb0ef743a40bed1bb3d2cbcfa23dc7..e41d4104d77021cae6438886bcb7015469d86a9f 100644 > --- a/drivers/clk/qcom/dispcc-sm8550.c > +++ b/drivers/clk/qcom/dispcc-sm8550.c > @@ -75,7 +75,7 @@ static struct pll_vco lucid_ole_vco[] = { > { 249600000, 2000000000, 0 }, > }; > > -static const struct alpha_pll_config disp_cc_pll0_config = { > +static struct alpha_pll_config disp_cc_pll0_config = { > .l = 0xd, > .alpha = 0x6492, > .config_ctl_val = 0x20485699, > @@ -106,7 +106,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { > }, > }; > > -static const struct alpha_pll_config disp_cc_pll1_config = { > +static struct alpha_pll_config disp_cc_pll1_config = { > .l = 0x1f, > .alpha = 0x4000, > .config_ctl_val = 0x20485699, > @@ -594,6 +594,13 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { > { } > }; > > +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = { > + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = { > F(19200000, P_BI_TCXO, 1, 0, 0), > F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > @@ -1750,6 +1757,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = { > }; > > static const struct of_device_id disp_cc_sm8550_match_table[] = { > + { .compatible = "qcom,sar2130p-dispcc" }, > { .compatible = "qcom,sm8550-dispcc" }, > { .compatible = "qcom,sm8650-dispcc" }, > { } > @@ -1780,6 +1788,12 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) > disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650; > disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = > &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { > + disp_cc_pll0_config.l = 0x1f; > + disp_cc_pll0_config.alpha = 0x4000; > + disp_cc_pll0_config.user_ctl_val = 0x1; > + disp_cc_pll1_config.user_ctl_val = 0x1; > + disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p; > } > > clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d..f314f26fe136c0fc1612edc0cca23c4deba5cd9f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -968,10 +968,10 @@ config SM_DISPCC_8450 config SM_DISPCC_8550 tristate "SM8550 Display Clock Controller" depends on ARM64 || COMPILE_TEST - depends on SM_GCC_8550 || SM_GCC_8650 + depends on SM_GCC_8550 || SM_GCC_8650 || SAR_GCC_2130P help Support for the display clock controller on Qualcomm Technologies, Inc - SM8550 or SM8650 devices. + SAR2130P, SM8550 or SM8650 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 7f9021ca0ecb0ef743a40bed1bb3d2cbcfa23dc7..e41d4104d77021cae6438886bcb7015469d86a9f 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -75,7 +75,7 @@ static struct pll_vco lucid_ole_vco[] = { { 249600000, 2000000000, 0 }, }; -static const struct alpha_pll_config disp_cc_pll0_config = { +static struct alpha_pll_config disp_cc_pll0_config = { .l = 0xd, .alpha = 0x6492, .config_ctl_val = 0x20485699, @@ -106,7 +106,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { }, }; -static const struct alpha_pll_config disp_cc_pll1_config = { +static struct alpha_pll_config disp_cc_pll1_config = { .l = 0x1f, .alpha = 0x4000, .config_ctl_val = 0x20485699, @@ -594,6 +594,13 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { { } }; +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = { + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), @@ -1750,6 +1757,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = { }; static const struct of_device_id disp_cc_sm8550_match_table[] = { + { .compatible = "qcom,sar2130p-dispcc" }, { .compatible = "qcom,sm8550-dispcc" }, { .compatible = "qcom,sm8650-dispcc" }, { } @@ -1780,6 +1788,12 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650; disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { + disp_cc_pll0_config.l = 0x1f; + disp_cc_pll0_config.alpha = 0x4000; + disp_cc_pll0_config.user_ctl_val = 0x1; + disp_cc_pll1_config.user_ctl_val = 0x1; + disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p; } clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
The display clock controller on SAR2130P is very close to the clock controller on SM8550 (and SM8650). Reuse existing driver to add support for the controller on SAR2130P. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/Kconfig | 4 ++-- drivers/clk/qcom/dispcc-sm8550.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-)