@@ -722,6 +722,11 @@ struct ath12k_pdev {
struct mlo_timestamp timestamp;
};
+struct cmem_remap {
+ u32 base;
+ u32 size;
+};
+
struct ath12k_fw_pdev {
u32 pdev_id;
u32 phy_id;
@@ -787,6 +792,8 @@ struct ath12k_base {
void __iomem *mem;
unsigned long mem_len;
+ void __iomem *mem_cmem;
+
struct {
enum ath12k_bus bus;
const struct ath12k_hif_ops *ops;
@@ -372,6 +372,10 @@ struct ath12k_base;
* ath12k_hal_rx_desc_get_err().
*/
+#define HAL_IPQ5332_CMEM_REG_BASE 0xC100000
+#define HAL_IPQ5332_CMEM_SIZE 0x40000
+#define HAL_IPQ5332_CMEM_BASE 0x100000
+
enum hal_srng_ring_id {
HAL_SRNG_RING_ID_REO2SW0 = 0,
HAL_SRNG_RING_ID_REO2SW1,
@@ -1223,6 +1223,11 @@ static const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = {
HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
};
+static const struct cmem_remap ath12k_cmem_remap_ipq5332 = {
+ .base = HAL_IPQ5332_CMEM_REG_BASE,
+ .size = HAL_IPQ5332_CMEM_SIZE,
+};
+
static const struct ath12k_hw_params ath12k_hw_params[] = {
{
.name = "qcn9274 hw1.0",
@@ -1301,6 +1306,7 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.supports_aspm = false,
.m3_fw_support = true,
+ .cmem_remap = NULL,
},
{
.name = "wcn7850 hw2.0",
@@ -1383,6 +1389,7 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.supports_aspm = true,
.m3_fw_support = true,
+ .cmem_remap = NULL,
},
{
.name = "qcn9274 hw2.0",
@@ -1461,6 +1468,7 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.supports_aspm = false,
.m3_fw_support = true,
+ .cmem_remap = NULL,
},
{
.name = "ipq5332 hw1.0",
@@ -1534,6 +1542,7 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.supports_aspm = false,
.m3_fw_support = false,
+ .cmem_remap = &ath12k_cmem_remap_ipq5332,
},
};
@@ -222,6 +222,7 @@ struct ath12k_hw_params {
u32 iova_mask;
bool m3_fw_support;
+ const struct cmem_remap *cmem_remap;
};
struct ath12k_hw_ops {