Message ID | 20241007-wrapped-keys-dts-v8-3-05ee041f2fc1@linaro.org |
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Mon, 07 Oct 2024 03:03:09 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:6100:637:cbe9:f3bc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f9384f648sm8498695e9.20.2024.10.07.03.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 03:03:08 -0700 (PDT) From: Bartosz Golaszewski <brgl@bgdev.pl> Date: Mon, 07 Oct 2024 12:02:57 +0200 Subject: [PATCH v8 3/3] arm64: dts: qcom: sa8775p: extend the register range for UFS ICE Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20241007-wrapped-keys-dts-v8-3-05ee041f2fc1@linaro.org> References: <20241007-wrapped-keys-dts-v8-0-05ee041f2fc1@linaro.org> In-Reply-To: <20241007-wrapped-keys-dts-v8-0-05ee041f2fc1@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konradybcio@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski <bartosz.golaszewski@linaro.org> X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 |
Series |
arm64: dts: qcom: extend the register range for ICE on several platforms
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expand
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diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index e8dbc8d820a6..82099d7d0472 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1908,7 +1908,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0x0 0x01d88000 0x0 0x8000>; + reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; };