| Message ID | 20240924100602.3813725-9-vladimir.zapolskiy@linaro.org |
|---|---|
| State | Accepted |
| Commit | 615ce95458a322b7bb16cba5cafaf10df80e3d6f |
| Headers | show |
| Series | arm64: dts: qcom: enable dispcc controllers by default | expand |
On 24/09/2024 12:06, Vladimir Zapolskiy wrote: > After a change enabling display clock controller for all Qualcomm SM8650 > powered board by default there is no more need to set a status property > of dispcc on SM8650-MTP board. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts > index c63822f5b127..0db2cb03f252 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts > @@ -585,10 +585,6 @@ vreg_l7n_3p3: ldo7 { > }; > }; > > -&dispcc { > - status = "okay"; > -}; > - > &lpass_tlmm { > spkr_1_sd_n_active: spkr-1-sd-n-active-state { > pins = "gpio21"; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index c63822f5b127..0db2cb03f252 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -585,10 +585,6 @@ vreg_l7n_3p3: ldo7 { }; }; -&dispcc { - status = "okay"; -}; - &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21";
After a change enabling display clock controller for all Qualcomm SM8650 powered board by default there is no more need to set a status property of dispcc on SM8650-MTP board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- 1 file changed, 4 deletions(-)