Message ID | 20240922120112.5067-1-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show |
On Sun, 22 Sept 2024 at 13:01, Richard Henderson <richard.henderson@linaro.org> wrote: > > The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb: > > Merge tag 'pull-target-arm-20240919' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-19 14:15:15 +0100) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240922 > > for you to fetch changes up to c4d80fa63e823dc8dbf094b29e39b6978a3073b6: > > linux-user: update syscall.tbl to Linux v6.11 (2024-09-22 09:30:18 +0200) > > ---------------------------------------------------------------- > target/ppc: Fix lxvx/stxvx facility check > linux-user: update syscall_nr.h to Linux v6.10 > linux-user: update syscall.tbl to Linux v6.11 > tcg: Fix iteration step in 32-bit gvec operation > tcg: Propagate new TCGOp to add_as_label_use > tcg/*: Do not expand cmp_vec, cmpsel_vec early > tcg/optimize: Fold movcond with true and false values identical > tcg/optimize: Optimize cmp_vec and cmpsel_vec > tcg/optimize: Optimize bitsel_vec > tcg/i386: Optimize cmpsel with constant 0 operand 3. > tcg/i386: Implement cmp_vec with avx512 insns > tcg/i386: Implement cmpsel_vec with avx512 insns > tcg/i386: Implement vector TST{EQ,NE} for avx512 > tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments > tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2 for any user-visible changes. -- PMM