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From: Qiang Yu <quic_qianyu@quicinc.com>
To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org,
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Subject: [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100
Date: Fri, 13 Sep 2024 01:37:21 -0700
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| Series |
Add support for PCIe3 on x1e80100
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expand
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diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index a9db0a231563..e2d6719ca54d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -70,6 +70,10 @@ properties: - const: pci # PCIe core reset - const: link_down # PCIe link down reset + operating-points-v2: true + opp-table: + type: object + allOf: - $ref: qcom,pcie-common.yaml#
Add OPP table so that PCIe is able to adjust power domain performance state and ICC peak bw according to PCIe gen speed and link width. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ 1 file changed, 4 insertions(+)