@@ -21,10 +21,10 @@
#include "qemu/main-loop.h"
#include "cpu.h"
#include "trace.h"
+#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "sysemu/runstate.h"
-
static const char * const excp_names[0x80] = {
[TT_TFAULT] = "Instruction Access Fault",
[TT_ILL_INSN] = "Illegal Instruction",
@@ -116,22 +116,9 @@ void sparc_cpu_do_interrupt(CPUState *cs)
qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
log_cpu_state(cs, 0);
-#if 0
- {
- int i;
- uint8_t *ptr;
-
- qemu_log(" code=");
- ptr = (uint8_t *)env->pc;
- for (i = 0; i < 16; i++) {
- qemu_log(" %02x", ldub(ptr + i));
- }
- qemu_log("\n");
- }
-#endif
count++;
}
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
if (env->psret == 0) {
if (cs->exception_index == 0x80 &&
env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
@@ -143,6 +130,29 @@ void sparc_cpu_do_interrupt(CPUState *cs)
}
return;
}
+ if (intno == TT_FP_EXCP) {
+ /*
+ * The sparc32 fpu has three states related to exception handling.
+ * The FPop that signals an exception transitions from fp_execute
+ * to fp_exception_pending. A subsequent FPop transitions from
+ * fp_exception_pending to fp_exception, which forces the trap.
+ *
+ * If the queue is not empty, this trap is due to execution of an
+ * illegal FPop while in fp_exception state. Here we are to
+ * re-enter fp_exception_pending state without queuing the insn.
+ *
+ * We do not model the fp_exception_pending state, but instead
+ * skip directly to fp_exception state. We advance pc/npc to
+ * mimic delayed trap delivery as if by the subsequent insn.
+ */
+ if (!env->fsr_qne) {
+ env->fsr_qne = FSR_QNE;
+ env->fq.s.addr = env->pc;
+ env->fq.s.insn = cpu_ldl_code(env, env->pc);
+ }
+ env->pc = env->npc;
+ env->npc = env->npc + 4;
+ }
#endif
env->psret = 0;
cwp = cpu_cwp_dec(env, env->cwp - 1);