| Message ID | 20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-1-bdb05b4b5a2e@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [01/21] drm/msm/dsi: add support to DSI CTRL v2.8.0 | expand |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 于2024年8月29日周四 18:35写道： > > On Thu, 29 Aug 2024 at 13:19, Jun Nie <jun.nie@linaro.org> wrote: > > > > From: Jonathan Marek <jonathan@marek.ca> > > > > Add support to DSI CTRL v2.8.0 with priority support > > Proper description is missing Actually, there is no clear doc for this register. Any URL or doc key word to search? > > > > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > Several tags are missing here. Co-develop and SoB tag, right? > > Also, how is this patch related to quadpipe? It is a must per test. Maybe it is just related to dual-DSI. We can have answer if 2:2:2 is enabled. - Jun
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 185d7de0bf376..6388bb12696ff 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2238,13 +2238,23 @@ int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, return ret; } +#define DSI_VBIF_CTRL (0x01CC - 4) +#define DSI_VBIF_CTRL_PRIORITY 0x07 + void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, u32 len) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; + u32 reg; dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); dsi_write(msm_host, REG_DSI_DMA_LEN, len); + if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_8_0) { + reg = dsi_read(msm_host, DSI_VBIF_CTRL); + reg |= (DSI_VBIF_CTRL_PRIORITY & 0x7); + dsi_write(msm_host, DSI_VBIF_CTRL, reg); + } dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); /* Make sure trigger happens */