diff mbox

[Linaro-uefi,19/28] Hisilicon: Remove unnesseary variable initializtion

Message ID 1479122995-50330-20-git-send-email-heyi.guo@linaro.org
State Superseded
Headers show

Commit Message

gary guo Nov. 14, 2016, 11:29 a.m. UTC
The variable will be initialized in the function code,
so it is not nesseary to be filled a data in the definition.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c  | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Leif Lindholm Nov. 15, 2016, 8:35 p.m. UTC | #1
On Mon, Nov 14, 2016 at 07:29:46PM +0800, Heyi Guo wrote:
> The variable will be initialized in the function code,
> so it is not nesseary to be filled a data in the definition.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c  | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
> index 005d28f..61473e8 100644
> --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
> +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
> @@ -226,7 +226,7 @@ GetCacheSocketStr (
>    OUT CHAR16    *CacheSocketStr
>    )
>  {
> -    UINTN CacheSocketStrLen = 0;
> +    UINTN CacheSocketStrLen;
>  
>      if(CacheLevel == CPU_CACHE_L1_Instruction)
>      {
> @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable (
>      CACHE_SRAM_TYPE_DATA        CacheSramType = {0};
>  
>      CoreCount = 16;     // Default value is 16 Core
> -    CacheSize = 0;
>  
>      //
>      // Set Cache Configuration
> -- 
> 1.9.1
>
diff mbox

Patch

diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 005d28f..61473e8 100644
--- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -226,7 +226,7 @@  GetCacheSocketStr (
   OUT CHAR16    *CacheSocketStr
   )
 {
-    UINTN CacheSocketStrLen = 0;
+    UINTN CacheSocketStrLen;
 
     if(CacheLevel == CPU_CACHE_L1_Instruction)
     {
@@ -258,7 +258,6 @@  UpdateSmbiosCacheTable (
     CACHE_SRAM_TYPE_DATA        CacheSramType = {0};
 
     CoreCount = 16;     // Default value is 16 Core
-    CacheSize = 0;
 
     //
     // Set Cache Configuration