| Message ID | 20240820-smmu-v3-1-2f71483b00ec@freebox.fr |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux | expand |
On Tue, Aug 20, 2024 at 03:27:19PM GMT, Marc Gonzalez wrote: > On qcom msm8998, writing to the last context bank of lpass_q6_smmu > (base address 0x05100000) produces a system freeze & reboot. > > The hardware/hypervisor reports 13 context banks for the LPASS SMMU > on msm8998, but only the first 12 are accessible... > Override the number of context banks > > [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... > [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: > [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation > [ 2.563627] arm-smmu 5100000.iommu: address translation ops > [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk > [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) > [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups > [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) > [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 > [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA > [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings > > Specifically, the crashes occur here: > > qsmmu->bypass_cbndx = smmu->num_context_banks - 1; > arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); > > and here: > > arm_smmu_write_context_bank(smmu, i); > arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); > > It is likely that FW reserves the last context bank for its own use, > thus a simple work-around is: DON'T USE IT in Linux. > > If we decrease the number of context banks, last one will be "hidden". > > Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Regards, Bjorn > --- > Changes in v3: > - Use very specific test (hack) to avoid changing the binding (Bjorn) > - Link to v2: https://lore.kernel.org/r/20240819-smmu-v1-0-bce6e4738825@freebox.fr > > Changes in v2: > - Use the compatible prop instead of a specific prop to trigger work-around (Bjorn & Caleb) > - Add qcom,msm8998-lpass-smmu compatible string > - Link to v1: https://lore.kernel.org/r/20240814-smmu-v1-0-3d6c27027d5b@freebox.fr > > On qcom msm8998, writing to the last context bank of lpass_q6_smmu > (base address 0x05100000) produces a system freeze & reboot. > > The hardware/hypervisor reports 13 context banks for the LPASS SMMU > on msm8998, but only the first 12 are accessible... > Override the number of context banks > > [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... > [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: > [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation > [ 2.563627] arm-smmu 5100000.iommu: address translation ops > [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk > [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) > [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups > [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) > [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 > [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA > [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings > > Specifically, here: > > qsmmu->bypass_cbndx = smmu->num_context_banks - 1; > arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); > > and here: > > arm_smmu_write_context_bank(smmu, i); > arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); > > It is likely that FW reserves the last context bank for its own use, > thus a simple work-around would be: DON'T USE IT in Linux. > > For reference, the lpass_q6_smmu node looks like this: > > lpass_q6_smmu: iommu@5100000 { > compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > reg = <0x05100000 0x40000>; > clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; > clock-names = "iface"; > > #global-interrupts = <0>; > #iommu-cells = <1>; > interrupts = > <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > > power-domains = <&gcc LPASS_ADSP_GDSC>; > status = "disabled"; > }; > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 7e65189ca7b8c..625db1d00fe5e 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -282,6 +282,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) > u32 smr; > int i; > > + /* > + * MSM8998 LPASS SMMU reports 13 context banks, but accessing > + * the last context bank crashes the system. > + */ > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) > + smmu->num_context_banks = 12; > + > /* > * Some platforms support more than the Arm SMMU architected maximum of > * 128 stream matching groups. For unknown reasons, the additional > > --- > base-commit: 96a96aed6bb75b5c212f233b6c059a9354cdeebe > change-id: 20240814-smmu-d572c1a16aac > > Best regards, > -- > Marc Gonzalez <mgonzalez@freebox.fr> >
On 20/08/2024 15:27, Marc Gonzalez wrote: > On qcom msm8998, writing to the last context bank of lpass_q6_smmu > (base address 0x05100000) produces a system freeze & reboot. > > The hardware/hypervisor reports 13 context banks for the LPASS SMMU > on msm8998, but only the first 12 are accessible... > Override the number of context banks > > [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... > [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: > [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation > [ 2.563627] arm-smmu 5100000.iommu: address translation ops > [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk > [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) > [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups > [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) > [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 > [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA > [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings > > Specifically, the crashes occur here: > > qsmmu->bypass_cbndx = smmu->num_context_banks - 1; > arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); > > and here: > > arm_smmu_write_context_bank(smmu, i); > arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); > > It is likely that FW reserves the last context bank for its own use, > thus a simple work-around is: DON'T USE IT in Linux. > > If we decrease the number of context banks, last one will be "hidden". > > Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> > --- > Changes in v3: > - Use very specific test (hack) to avoid changing the binding (Bjorn) > - Link to v2: https://lore.kernel.org/r/20240819-smmu-v1-0-bce6e4738825@freebox.fr > > Changes in v2: > - Use the compatible prop instead of a specific prop to trigger work-around (Bjorn & Caleb) > - Add qcom,msm8998-lpass-smmu compatible string > - Link to v1: https://lore.kernel.org/r/20240814-smmu-v1-0-3d6c27027d5b@freebox.fr > > On qcom msm8998, writing to the last context bank of lpass_q6_smmu > (base address 0x05100000) produces a system freeze & reboot. > > The hardware/hypervisor reports 13 context banks for the LPASS SMMU > on msm8998, but only the first 12 are accessible... > Override the number of context banks > > [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... > [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: > [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation > [ 2.563627] arm-smmu 5100000.iommu: address translation ops > [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk > [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) > [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups > [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) > [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 > [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA > [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings > > Specifically, here: > > qsmmu->bypass_cbndx = smmu->num_context_banks - 1; > arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); > > and here: > > arm_smmu_write_context_bank(smmu, i); > arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); > > It is likely that FW reserves the last context bank for its own use, > thus a simple work-around would be: DON'T USE IT in Linux. > > For reference, the lpass_q6_smmu node looks like this: > > lpass_q6_smmu: iommu@5100000 { > compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > reg = <0x05100000 0x40000>; > clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; > clock-names = "iface"; > > #global-interrupts = <0>; > #iommu-cells = <1>; > interrupts = > <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > > power-domains = <&gcc LPASS_ADSP_GDSC>; > status = "disabled"; > }; > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 7e65189ca7b8c..625db1d00fe5e 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -282,6 +282,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) > u32 smr; > int i; > > + /* > + * MSM8998 LPASS SMMU reports 13 context banks, but accessing > + * the last context bank crashes the system. > + */ > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) > + smmu->num_context_banks = 12; > + > /* > * Some platforms support more than the Arm SMMU architected maximum of > * 128 stream matching groups. For unknown reasons, the additional > > --- > base-commit: 96a96aed6bb75b5c212f233b6c059a9354cdeebe > change-id: 20240814-smmu-d572c1a16aac > > Best regards,
On Tue, 20 Aug 2024 15:27:19 +0200, Marc Gonzalez wrote: > On qcom msm8998, writing to the last context bank of lpass_q6_smmu > (base address 0x05100000) produces a system freeze & reboot. > > The hardware/hypervisor reports 13 context banks for the LPASS SMMU > on msm8998, but only the first 12 are accessible... > Override the number of context banks > > [...] Applied to will (for-joerg/arm-smmu/updates), thanks! [1/1] iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux https://git.kernel.org/will/c/3a8990b8a778 Cheers,
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7e65189ca7b8c..625db1d00fe5e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -282,6 +282,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) u32 smr; int i; + /* + * MSM8998 LPASS SMMU reports 13 context banks, but accessing + * the last context bank crashes the system. + */ + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) + smmu->num_context_banks = 12; + /* * Some platforms support more than the Arm SMMU architected maximum of * 128 stream matching groups. For unknown reasons, the additional
On qcom msm8998, writing to the last context bank of lpass_q6_smmu (base address 0x05100000) produces a system freeze & reboot. The hardware/hypervisor reports 13 context banks for the LPASS SMMU on msm8998, but only the first 12 are accessible... Override the number of context banks [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation [ 2.563627] arm-smmu 5100000.iommu: address translation ops [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings Specifically, the crashes occur here: qsmmu->bypass_cbndx = smmu->num_context_banks - 1; arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); and here: arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); It is likely that FW reserves the last context bank for its own use, thus a simple work-around is: DON'T USE IT in Linux. If we decrease the number of context banks, last one will be "hidden". Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> --- Changes in v3: - Use very specific test (hack) to avoid changing the binding (Bjorn) - Link to v2: https://lore.kernel.org/r/20240819-smmu-v1-0-bce6e4738825@freebox.fr Changes in v2: - Use the compatible prop instead of a specific prop to trigger work-around (Bjorn & Caleb) - Add qcom,msm8998-lpass-smmu compatible string - Link to v1: https://lore.kernel.org/r/20240814-smmu-v1-0-3d6c27027d5b@freebox.fr On qcom msm8998, writing to the last context bank of lpass_q6_smmu (base address 0x05100000) produces a system freeze & reboot. The hardware/hypervisor reports 13 context banks for the LPASS SMMU on msm8998, but only the first 12 are accessible... Override the number of context banks [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation [ 2.563627] arm-smmu 5100000.iommu: address translation ops [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings Specifically, here: qsmmu->bypass_cbndx = smmu->num_context_banks - 1; arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); and here: arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); It is likely that FW reserves the last context bank for its own use, thus a simple work-around would be: DON'T USE IT in Linux. For reference, the lpass_q6_smmu node looks like this: lpass_q6_smmu: iommu@5100000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x05100000 0x40000>; clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; clock-names = "iface"; #global-interrupts = <0>; #iommu-cells = <1>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&gcc LPASS_ADSP_GDSC>; status = "disabled"; }; --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 +++++++ 1 file changed, 7 insertions(+) --- base-commit: 96a96aed6bb75b5c212f233b6c059a9354cdeebe change-id: 20240814-smmu-d572c1a16aac Best regards,