| Message ID | AM9PR04MB850617C07DDFFEA551622F58E2832@AM9PR04MB8506.eurprd04.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/7] net: driver: stmmac: extend CSR calc support | expand |
On 8/18/2024 2:52 PM, Jan Petrous (OSS) wrote: > The PTP clock is read by stmmac_platform during DT parse. > On S32G/R the clock is not ready and returns 0. Postpone > reading of the clock on PTP init. > Ah, I see. So the clock returns zero into the hardware bits accessed by stmmac_platform. Then you come back in and fill this in later during the dwmac_probe. Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c index 8daa01d01f29..92c51005cbed 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c @@ -149,6 +149,18 @@ static void s32cc_fix_mac_speed(void *priv, unsigned int speed, unsigned int mod dev_err(gmac->dev, "Can't set tx clock\n"); } +static void s32cc_gmac_ptp_clk_freq_config(struct stmmac_priv *priv) +{ + struct plat_stmmacenet_data *plat = priv->plat; + + if (!plat->clk_ptp_ref) + return; + + plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref); + + netdev_dbg(priv->dev, "PTP rate %lu\n", plat->clk_ptp_rate); +} + static int s32cc_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -204,6 +216,7 @@ static int s32cc_dwmac_probe(struct platform_device *pdev) plat->init = s32cc_gmac_init; plat->exit = s32cc_gmac_exit; plat->fix_mac_speed = s32cc_fix_mac_speed; + plat->ptp_clk_freq_config = s32cc_gmac_ptp_clk_freq_config; plat->bsp_priv = gmac;