[PULL,16/20] target/sparc: Restrict STQF to sparcv9

Message ID	20240819225116.17928-17-philmd@linaro.org
State	Accepted
Commit	12d36294a2d978faf893101862118d1ac1815e85
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson <richard.henderson@linaro.org>, qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 16/20] target/sparc: Restrict STQF to sparcv9 Date: Tue, 20 Aug 2024 00:51:12 +0200 Message-ID: <20240819225116.17928-17-philmd@linaro.org> In-Reply-To: <20240819225116.17928-1-philmd@linaro.org> References: <20240819225116.17928-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/20] hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineState \| expand [PULL,01/20] hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineState [PULL,02/20] hw/mips/loongson3_virt: Fix condition of IPI IOCSR connection [PULL,03/20] qemu-options.hx: correct formatting -smbios type=4 [PULL,04/20] target/mips: Pass page table entry size as MemOp to get_pte() [PULL,05/20] target/mips: Use correct MMU index in get_pte() [PULL,06/20] target/mips: Load PTE as DATA [PULL,07/20] hw/dma/xilinx_axidma: Use semicolon at end of statement, not comma [PULL,08/20] hw/remote/message.c: Don't directly invoke DeviceClass:reset [PULL,09/20] linux-user/mips: Do not try to use removed R5900 CPU [PULL,10/20] linux-user/mips: Select Octeon68XX CPU for Octeon binaries [PULL,11/20] linux-user/mips: Select MIPS64R2-generic for Rel2 binaries [PULL,12/20] linux-user/mips: Select Loongson CPU for Loongson binaries [PULL,13/20] tests/avocado: exec_command should not consume console output [PULL,14/20] tests/avocado: Mark ppc_hv_tests.py as non-flaky after fixed console interaction [PULL,15/20] contrib/plugins/execlog: Fix shadowed declaration warning [PULL,16/20] target/sparc: Restrict STQF to sparcv9 [PULL,17/20] hw/ppc/Kconfig: Add missing SERIAL_ISA dependency to POWERNV machine [PULL,18/20] hw/i386/pc: Unify vmport=auto handling [PULL,19/20] hw/i386/pc: Ensure vmport prerequisites are fulfilled [PULL,20/20] crypto/tlscredspsk: Free username on finalize

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20240819225116.17928-17-philmd@linaro.org

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12d36294a2d978faf893101862118d1ac1815e85

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Subject: [PULL 16/20] target/sparc: Restrict STQF to sparcv9
Date: Tue, 20 Aug 2024 00:51:12 +0200
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Series

[PULL,01/20] hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineState | expand

Commit Message

Philippe Mathieu-Daudé Aug. 19, 2024, 10:51 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Prior to sparcv9, the same encoding was STDFQ.

Cc: qemu-stable@nongnu.org
Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sparc/insns.decode | 2 +-
 target/sparc/translate.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index fbcb4f7aef..5fd478191a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -644,7 +644,7 @@  STF         11 ..... 100100 ..... . .............          @r_r_ri_na
 STFSR       11 00000 100101 ..... . .............          @n_r_ri
 STXFSR      11 00001 100101 ..... . .............          @n_r_ri
 {
-  STQF      11 ..... 100110 ..... . .............          @q_r_ri_na
+  STQF      11 ..... 100110 ..... . .............          @q_r_ri_na # v9
   STDFQ     11 ----- 100110 ----- - -------------
 }
 STDF        11 ..... 100111 ..... . .............          @d_r_ri_na
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 113639083b..c803e8d1ba 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4521,7 +4521,7 @@  static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
 
 TRANS(STF, ALL, do_st_fpr, a, MO_32)
 TRANS(STDF, ALL, do_st_fpr, a, MO_64)
-TRANS(STQF, ALL, do_st_fpr, a, MO_128)
+TRANS(STQF, 64, do_st_fpr, a, MO_128)
 
 TRANS(STFA, 64, do_st_fpr, a, MO_32)
 TRANS(STDFA, 64, do_st_fpr, a, MO_64)

[PULL,16/20] target/sparc: Restrict STQF to sparcv9

Commit Message

Patch