diff mbox series

[2/4] clk/qcom: sdm845: add dump data

Message ID 20240819-b4-qcom-clk-dump-v1-2-182cf77c23a2@linaro.org
State New
Headers show
Series clk/qcom: implement clk dump callback | expand

Commit Message

Caleb Connolly Aug. 19, 2024, 7:34 p.m. UTC 
Add debug data to dump PLL and RCG clocks.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-sdm845.c | 93 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index f41f8c9e8dee..adffb0cb2402 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -202,8 +202,96 @@  static const struct qcom_power_map sdm845_gdscs[] = {
 	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
 	[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
 };
 
+static const phys_addr_t sdm845_gpll_addrs[] = {
+	0x00100000, // GCC_GPLL0_MODE
+	0x00101000, // GCC_GPLL1_MODE
+	0x00102000, // GCC_GPLL2_MODE
+	0x00103000, // GCC_GPLL3_MODE
+	0x00176000, // GCC_GPLL4_MODE
+	0x00174000, // GCC_GPLL5_MODE
+	0x00113000, // GCC_GPLL6_MODE
+};
+
+static const phys_addr_t sdm845_rcg_addrs[] = {
+	0x0010f018, // GCC_USB30_PRIM_MASTER
+	0x0010f030, // GCC_USB30_PRIM_MOCK_UTMI
+	0x0010f05c, // GCC_USB3_PRIM_PHY_AUX
+	0x00110018, // GCC_USB30_SEC_MASTER
+	0x00110030, // GCC_USB30_SEC_MOCK_UTMI
+	0x0011005c, // GCC_USB3_SEC_PHY_AUX
+	0x0011400c, // GCC_SDCC2_APPS
+	0x0011600c, // GCC_SDCC4_APPS
+	0x00117018, // GCC_QUPV3_WRAP0_CORE_2X
+	0x00117034, // GCC_QUPV3_WRAP0_S0
+	0x00117164, // GCC_QUPV3_WRAP0_S1
+	0x00117294, // GCC_QUPV3_WRAP0_S2
+	0x001173c4, // GCC_QUPV3_WRAP0_S3
+	0x001174f4, // GCC_QUPV3_WRAP0_S4
+	0x00117624, // GCC_QUPV3_WRAP0_S5
+	0x00117754, // GCC_QUPV3_WRAP0_S6
+	0x00117884, // GCC_QUPV3_WRAP0_S7
+	0x00118018, // GCC_QUPV3_WRAP1_S0
+	0x00118148, // GCC_QUPV3_WRAP1_S1
+	0x00118278, // GCC_QUPV3_WRAP1_S2
+	0x001183a8, // GCC_QUPV3_WRAP1_S3
+	0x001184d8, // GCC_QUPV3_WRAP1_S4
+	0x00118608, // GCC_QUPV3_WRAP1_S5
+	0x00118738, // GCC_QUPV3_WRAP1_S6
+	0x00118868, // GCC_QUPV3_WRAP1_S7
+	0x0016b028, // GCC_PCIE_0_AUX
+	0x0018d028, // GCC_PCIE_1_AUX
+	0x0016f014, // GCC_PCIE_PHY_REFGEN
+	0x0017501c, // GCC_UFS_CARD_AXI
+	0x0017505c, // GCC_UFS_CARD_ICE_CORE
+	0x00175074, // GCC_UFS_CARD_UNIPRO_CORE
+	0x00175090, // GCC_UFS_CARD_PHY_AUX
+	0x0017701c, // GCC_UFS_PHY_AXI
+	0x0017705c, // GCC_UFS_PHY_ICE_CORE
+	0x00177074, // GCC_UFS_PHY_UNIPRO_CORE
+	0x00177090, // GCC_UFS_PHY_PHY_AUX
+};
+
+static const char *const sdm845_rcg_names[] = {
+	"GCC_USB30_PRIM_MASTER",
+	"GCC_USB30_PRIM_MOCK_UTMI",
+	"GCC_USB3_PRIM_PHY_AUX",
+	"GCC_USB30_SEC_MASTER",
+	"GCC_USB30_SEC_MOCK_UTMI",
+	"GCC_USB3_SEC_PHY_AUX",
+	"GCC_SDCC2_APPS",
+	"GCC_SDCC4_APPS",
+	"GCC_QUPV3_WRAP0_CORE_2X",
+	"GCC_QUPV3_WRAP0_S0",
+	"GCC_QUPV3_WRAP0_S1",
+	"GCC_QUPV3_WRAP0_S2",
+	"GCC_QUPV3_WRAP0_S3",
+	"GCC_QUPV3_WRAP0_S4",
+	"GCC_QUPV3_WRAP0_S5",
+	"GCC_QUPV3_WRAP0_S6",
+	"GCC_QUPV3_WRAP0_S7",
+	"GCC_QUPV3_WRAP1_S0",
+	"GCC_QUPV3_WRAP1_S1",
+	"GCC_QUPV3_WRAP1_S2",
+	"GCC_QUPV3_WRAP1_S3",
+	"GCC_QUPV3_WRAP1_S4",
+	"GCC_QUPV3_WRAP1_S5",
+	"GCC_QUPV3_WRAP1_S6",
+	"GCC_QUPV3_WRAP1_S7",
+	"GCC_PCIE_0_AUX",
+	"GCC_PCIE_1_AUX",
+	"GCC_PCIE_PHY_REFGEN",
+	"GCC_UFS_CARD_AXI",
+	"GCC_UFS_CARD_ICE_CORE",
+	"GCC_UFS_CARD_UNIPRO_CORE",
+	"GCC_UFS_CARD_PHY_AUX",
+	"GCC_UFS_PHY_AXI",
+	"GCC_UFS_PHY_ICE_CORE",
+	"GCC_UFS_PHY_UNIPRO_CORE",
+	"GCC_UFS_PHY_PHY_AUX",
+};
+
 static struct msm_clk_data sdm845_clk_data = {
 	.resets = sdm845_gcc_resets,
 	.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
 	.clks = sdm845_clks,
@@ -212,8 +300,13 @@  static struct msm_clk_data sdm845_clk_data = {
 	.num_power_domains = ARRAY_SIZE(sdm845_gdscs),
 
 	.enable = sdm845_clk_enable,
 	.set_rate = sdm845_clk_set_rate,
+	.dbg_pll_addrs = sdm845_gpll_addrs,
+	.num_plls = ARRAY_SIZE(sdm845_gpll_addrs),
+	.dbg_rcg_addrs = sdm845_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sdm845_rcg_addrs),
+	.dbg_rcg_names = sdm845_rcg_names,
 };
 
 static const struct udevice_id gcc_sdm845_of_match[] = {
 	{