| Message ID | ejeph4wspggkmvhl7qmpvw5jlojyvma7epqd67i6vk5p6fncrk@de56nvgi6vzi |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add initial DTS for Samsung Galaxy Book4 Edge | expand |
On 24-08-15 13:54:01, Marcus Glocker wrote: > On Thu, Aug 15, 2024 at 01:47:23PM +0300, Abel Vesa wrote: > > > On 24-08-15 12:42:29, Marcus Glocker wrote: > > > Add the UFS Host Controller node. This was basically copied from the > > > arch/arm64/boot/dts/qcom/sc7180.dtsi file. > > > > > > Signed-off-by: Marcus Glocker <marcus@nazgul.ch> > > > --- > > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 71 ++++++++++++++++++++++++++ > > > 1 file changed, 71 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > index 7bca5fcd7d52..235e20e4b51f 100644 > > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > > @@ -2878,6 +2878,77 @@ mmss_noc: interconnect@1780000 { > > > #interconnect-cells = <2>; > > > }; > > > > > > + ufs_mem_hc: ufs@1d84000 { > > > + compatible = "qcom,x1e80100-ufshc", "qcom,ufshc", > > > + "jedec,ufs-2.0"; > > > + reg = <0 0x01d84000 0 0x3000>; > > > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > > > + phys = <&ufs_mem_phy>; > > > + phy-names = "ufsphy"; > > > + lanes-per-direction = <1>; > > > + #reset-cells = <1>; > > > + resets = <&gcc GCC_UFS_PHY_BCR>; > > > + reset-names = "rst"; > > > + > > > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > > > + > > > + iommus = <&apps_smmu 0xa0 0x0>; > > > + > > > + clock-names = "core_clk", > > > + "bus_aggr_clk", > > > + "iface_clk", > > > + "core_clk_unipro", > > > + "ref_clk", > > > + "tx_lane0_sync_clk", > > > + "rx_lane0_sync_clk"; > > > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > > > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > > > + <&gcc GCC_UFS_PHY_AHB_CLK>, > > > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > > > + <&rpmhcc RPMH_CXO_CLK>, > > > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > > > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; > > > + freq-table-hz = <50000000 200000000>, > > > + <0 0>, > > > + <0 0>, > > > + <37500000 150000000>, > > > + <0 0>, > > > + <0 0>, > > > + <0 0>; > > > + > > > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > > > + interconnect-names = "ufs-ddr", "cpu-ufs"; > > > + > > > + qcom,ice = <&ice>; > > > + > > > + status = "disabled"; > > > + }; > > > + > > > + ufs_mem_phy: phy@1d87000 { > > > + compatible = "qcom,x1e80100-qmp-ufs-phy"; > > > > Can't find any phy patch that adds this compatible to the driver. > > That might well be, since this is pretty new hardware. But the goal > of this submission is only to describe the hardware, not to add > immediate support to the OS drivers. Whether the drivers will make use > of it, is a different story, and up to the people who maintain the > respective drivers. > > Getting the right DTB in, at least opens the possibility to continue > development in the driver area to further support this new hardware. > > But I won't touch your drivers, not my goal. Presumably, you do have the UFS working on your Book4 laptop, right? If so, I would expect you do have the PHY working as well and therefore a patch that adds the X Elite compatible, right? > > > > + reg = <0 0x01d87000 0 0x1000>; > > > + clocks = <&rpmhcc RPMH_CXO_CLK>, > > > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > > > + clock-names = "ref", > > > + "ref_aux", > > > + "qref"; > > > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > > > + resets = <&ufs_mem_hc 0>; > > > + reset-names = "ufsphy"; > > > + #phy-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + ice: crypto@1d90000 { > > > + compatible = "qcom,x1e80100-inline-crypto-engine", > > > + "qcom,inline-crypto-engine"; > > > + reg = <0 0x01d90000 0 0x8000>; > > > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > > > + }; > > > + > > > pcie6a: pci@1bf8000 { > > > device_type = "pci"; > > > compatible = "qcom,pcie-x1e80100"; > > > -- > > > 2.39.2 > > >
On 15/08/2024 18:59, Marcus Glocker wrote: >>> Getting the right DTB in, at least opens the possibility to continue >>> development in the driver area to further support this new hardware. >>> >>> But I won't touch your drivers, not my goal. >> >> Presumably, you do have the UFS working on your Book4 laptop, right? > > That's right, but ... > >> If so, I would expect you do have the PHY working as well and therefore >> a patch that adds the X Elite compatible, right? > > ... I'm not using Linux on that laptop but OpenBSD. Hence, my UFS > driver patch will be useless for you. If one of your developers gets > his hand on that laptop, enabling UFS based on that DTB should be > fairly straight forward. > > The reason why we are interested to get new DTS' in your tree, is > because we're using the Linux DTS tree as a base, and then patch over > it as of our requirements. The less patches we need to apply, the > easier the maintenance is. That's fine. You do not need drivers implementing bindings and DTS in general. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 15/08/2024 12:42, Marcus Glocker wrote: > Add the UFS Host Controller node. This was basically copied from the > arch/arm64/boot/dts/qcom/sc7180.dtsi file. > > Signed-off-by: Marcus Glocker <marcus@nazgul.ch> > + > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,x1e80100-qmp-ufs-phy"; > + reg = <0 0x01d87000 0 0x1000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + clock-names = "ref", > + "ref_aux", > + "qref"; One does not match the other. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7bca5fcd7d52..235e20e4b51f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2878,6 +2878,77 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,x1e80100-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xa0 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ice = <&ice>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,x1e80100-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + pcie6a: pci@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100";
Add the UFS Host Controller node. This was basically copied from the arch/arm64/boot/dts/qcom/sc7180.dtsi file. Signed-off-by: Marcus Glocker <marcus@nazgul.ch> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+)