| Message ID | 20240813152054.2445099-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 8/14/24 01:20, Peter Maydell wrote: > Three last bugfixes to sneak into rc2 if we can. The fix > for the EL3-is-AArch32-and-we-run-code-at-EL0 bug is the > most important one here I think (though also the most risky). > > thanks > -- PMM > > The following changes since commit 9eb51530c12ae645b91e308d16196c68563ea883: > > Merge tag 'block-pull-request' ofhttps://gitlab.com/stefanha/qemu into staging (2024-08-13 07:59:32 +1000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240813 > > for you to fetch changes up to 4c2c0474693229c1f533239bb983495c5427784d: > > target/arm: Fix usage of MMU indexes when EL3 is AArch32 (2024-08-13 11:44:53 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values > * target/arm: Clear high SVE elements in handle_vec_simd_wshli > * target/arm: Fix usage of MMU indexes when EL3 is AArch32 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
Three last bugfixes to sneak into rc2 if we can. The fix for the EL3-is-AArch32-and-we-run-code-at-EL0 bug is the most important one here I think (though also the most risky). thanks -- PMM The following changes since commit 9eb51530c12ae645b91e308d16196c68563ea883: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-08-13 07:59:32 +1000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240813 for you to fetch changes up to 4c2c0474693229c1f533239bb983495c5427784d: target/arm: Fix usage of MMU indexes when EL3 is AArch32 (2024-08-13 11:44:53 +0100) ---------------------------------------------------------------- target-arm queue: * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values * target/arm: Clear high SVE elements in handle_vec_simd_wshli * target/arm: Fix usage of MMU indexes when EL3 is AArch32 ---------------------------------------------------------------- Peter Maydell (2): target/arm: Update translation regime comment for new features target/arm: Fix usage of MMU indexes when EL3 is AArch32 Richard Henderson (1): target/arm: Clear high SVE elements in handle_vec_simd_wshli Zheyu Ma (1): hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values target/arm/cpu.h | 50 +++++++++++++++++++++++++++--------------- target/arm/internals.h | 27 +++++++++++++++++++---- target/arm/tcg/translate.h | 2 ++ hw/misc/stm32l4x5_rcc.c | 28 ++++++++++++++++------- target/arm/helper.c | 34 ++++++++++++++++++---------- target/arm/ptw.c | 6 ++++- target/arm/tcg/hflags.c | 4 ++++ target/arm/tcg/translate-a64.c | 3 ++- target/arm/tcg/translate.c | 9 ++++---- 9 files changed, 116 insertions(+), 47 deletions(-)