diff mbox series

[2/4] clk: qcom: Add common PLL clock controller driver for IPQ SoC

Message ID 20240808-qcom_ipq_cmnpll-v1-2-b0631dcbf785@quicinc.com
State New
Headers show
Series Add common PLL clock controller driver for IPQ9574 | expand

Commit Message

Luo Jie Aug. 8, 2024, 2:03 p.m. UTC 
The common PLL clock controller driver supplies clocks to the
hardware blocks that together make up the Ethernet function
on Qualcomm IPQ SoCs. The driver is initially supported for
IPQ9574 SoC.

The common PLL clock controller expects a reference input clock
from the on-board Wi-Fi block acting as clock source. The input
reference clock needs to be configured to one of the supported
clock rates.

The controller supplies a number of fixed-rate output clocks.
For the IPQ9574, there is one output clock of 353 MHZ to PPE
(Packet Process Engine) hardware block, three 50 MHZ output
clocks and an additional 25 MHZ output clock supplied to the
connected Ethernet devices.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/clk/qcom/Kconfig           |  10 ++
 drivers/clk/qcom/Makefile          |   1 +
 drivers/clk/qcom/clk-ipq-cmn-pll.c | 233 +++++++++++++++++++++++++++++++++++++
 3 files changed, 244 insertions(+)

Comments

kernel test robot Aug. 10, 2024, 11:53 p.m. UTC | #1 
Hi Luo,

kernel test robot noticed the following build errors:

[auto build test ERROR on 222a3380f92b8791d4eeedf7cd750513ff428adf]

url:    https://github.com/intel-lab-lkp/linux/commits/Luo-Jie/dt-bindings-clock-qcom-Add-common-PLL-clock-controller-for-IPQ-SoC/20240808-221059
base:   222a3380f92b8791d4eeedf7cd750513ff428adf
patch link:    https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-2-b0631dcbf785%40quicinc.com
patch subject: [PATCH 2/4] clk: qcom: Add common PLL clock controller driver for IPQ SoC
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20240811/202408110756.rSXn1ZRu-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240811/202408110756.rSXn1ZRu-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408110756.rSXn1ZRu-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/clk/qcom/clk-ipq-cmn-pll.c: In function 'ipq_cmn_pll_config':
>> drivers/clk/qcom/clk-ipq-cmn-pll.c:96:24: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
      96 |                 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
         |                        ^~~~~~~~~~


vim +/FIELD_PREP +96 drivers/clk/qcom/clk-ipq-cmn-pll.c

    77	
    78	static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
    79	{
    80		void __iomem *base;
    81		u32 val;
    82	
    83		base = devm_of_iomap(dev, dev->of_node, 0, NULL);
    84		if (IS_ERR(base))
    85			return PTR_ERR(base);
    86	
    87		val = readl(base + CMN_PLL_REFCLK_CONFIG);
    88		val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
    89	
    90		/*
    91		 * Configure the reference input clock selection as per the given rate.
    92		 * The output clock rates are always of fixed value.
    93		 */
    94		switch (parent_rate) {
    95		case 25000000:
  > 96			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
    97			break;
    98		case 31250000:
    99			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4);
   100			break;
   101		case 40000000:
   102			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6);
   103			break;
   104		case 48000000:
   105			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
   106			break;
   107		case 50000000:
   108			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
   109			break;
   110		case 96000000:
   111			val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
   112			val &= ~CMN_PLL_REFCLK_DIV;
   113			val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
   114			break;
   115		default:
   116			return -EINVAL;
   117		}
   118	
   119		writel(val, base + CMN_PLL_REFCLK_CONFIG);
   120	
   121		/* Update the source clock rate selection. Only 96 MHZ uses 0. */
   122		val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION);
   123		val &= ~CMN_PLL_REFCLK_SRC_DIV;
   124		if (parent_rate != 96000000)
   125			val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1);
   126	
   127		writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION);
   128	
   129		/*
   130		 * Reset the common PLL block by asserting/de-asserting for 100 ms
   131		 * each, to ensure the updated configurations take effect.
   132		 */
   133		val = readl(base + CMN_PLL_POWER_ON_AND_RESET);
   134		val &= ~CMN_ANA_EN_SW_RSTN;
   135		writel(val, base);
   136		msleep(100);
   137	
   138		val |= CMN_ANA_EN_SW_RSTN;
   139		writel(val, base + CMN_PLL_POWER_ON_AND_RESET);
   140		msleep(100);
   141	
   142		return 0;
   143	}
   144
diff mbox series

Patch

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cf6ad908327f..8e36cde64134 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -190,6 +190,16 @@  config IPQ_APSS_6018
 	  Say Y if you want to support CPU frequency scaling on
 	  ipq based devices.
 
+config IPQ_CMN_PLL
+	tristate "IPQ Common PLL Clock Controller"
+	depends on IPQ_GCC_9574
+	help
+	  Support for common PLL clock controller on IPQ platform. The
+	  common PLL feeds the reference clocks to the Ethernet devices
+	  based on IPQ SoC.
+	  Say Y or M if you want to support common PLL clock on the IPQ
+	  based devices.
+
 config IPQ_GCC_4019
 	tristate "IPQ4019 Global Clock Controller"
 	help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 8a6f0dabd02f..35f656146de7 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -29,6 +29,7 @@  obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
 obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
 obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
 obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
+obj-$(CONFIG_IPQ_CMN_PLL) += clk-ipq-cmn-pll.o
 obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
 obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
diff --git a/drivers/clk/qcom/clk-ipq-cmn-pll.c b/drivers/clk/qcom/clk-ipq-cmn-pll.c
new file mode 100644
index 000000000000..c10c6a7e82e6
--- /dev/null
+++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
@@ -0,0 +1,233 @@ 
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/*
+ * Common PLL block expects the reference clock from on-board Wi-Fi block,
+ * and supplies the fixed rate clocks as output to the Ethernet hardware
+ * blocks. The Ethernet related blocks include PPE (packet process engine)
+ * and the external connected PHY (or switch) chip receiving clocks from
+ * the common PLL.
+ *
+ * On the IPQ9574 SoC, There are three clocks with 50 MHZ, one clock with
+ * 25 MHZ which are output from the common PLL to Ethernet PHY (or switch),
+ * and one clock with 353 MHZ to PPE.
+ *
+ *               +---------+
+ *               |   GCC   |
+ *               +--+---+--+
+ *           AHB CLK|   |SYS CLK
+ *                  V   V
+ *          +-------+---+------+
+ *          |                  +-------------> eth0-50mhz
+ * REF CLK  |     IPQ9574      |
+ * -------->+                  +-------------> eth1-50mhz
+ *          |  CMN PLL block   |
+ *          |                  +-------------> eth2-50mhz
+ *          |                  |
+ *          +---------+--------+-------------> eth-25mhz
+ *                    |
+ *                    V
+ *                    ppe-353mhz
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define CMN_PLL_REFCLK_SRC_SELECTION		0x28
+#define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
+
+#define CMN_PLL_REFCLK_CONFIG			0x784
+#define CMN_PLL_REFCLK_EXTERNAL			BIT(9)
+#define CMN_PLL_REFCLK_DIV			GENMASK(8, 4)
+#define CMN_PLL_REFCLK_INDEX			GENMASK(3, 0)
+
+#define CMN_PLL_POWER_ON_AND_RESET		0x780
+#define CMN_ANA_EN_SW_RSTN			BIT(6)
+
+/**
+ * struct cmn_pll_fixed_clk - Common PLL output clocks information
+ * @nrates:	Number of elements in rates
+ * @rates:	Array of clock rates supplied by common PLL
+ */
+struct cmn_pll_fixed_clk {
+	int nrates;
+	const unsigned long *rates;
+};
+
+/*
+ * The clock rates are for the output clock ppe-353mhz, eth0-50mhz
+ * eth1-50mhz, eth2-50mhz and eth-25mhz.
+ */
+static const unsigned long ipq9574_rates[] = {
+	353000000UL, 50000000UL, 50000000UL, 50000000UL, 25000000UL,
+};
+
+static const struct cmn_pll_fixed_clk ipq9574_fixed_clk = {
+	.nrates = ARRAY_SIZE(ipq9574_rates),
+	.rates = ipq9574_rates,
+};
+
+static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
+{
+	void __iomem *base;
+	u32 val;
+
+	base = devm_of_iomap(dev, dev->of_node, 0, NULL);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	val = readl(base + CMN_PLL_REFCLK_CONFIG);
+	val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
+
+	/*
+	 * Configure the reference input clock selection as per the given rate.
+	 * The output clock rates are always of fixed value.
+	 */
+	switch (parent_rate) {
+	case 25000000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
+		break;
+	case 31250000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4);
+		break;
+	case 40000000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6);
+		break;
+	case 48000000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
+		break;
+	case 50000000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
+		break;
+	case 96000000:
+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
+		val &= ~CMN_PLL_REFCLK_DIV;
+		val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	writel(val, base + CMN_PLL_REFCLK_CONFIG);
+
+	/* Update the source clock rate selection. Only 96 MHZ uses 0. */
+	val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION);
+	val &= ~CMN_PLL_REFCLK_SRC_DIV;
+	if (parent_rate != 96000000)
+		val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1);
+
+	writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION);
+
+	/*
+	 * Reset the common PLL block by asserting/de-asserting for 100 ms
+	 * each, to ensure the updated configurations take effect.
+	 */
+	val = readl(base + CMN_PLL_POWER_ON_AND_RESET);
+	val &= ~CMN_ANA_EN_SW_RSTN;
+	writel(val, base);
+	msleep(100);
+
+	val |= CMN_ANA_EN_SW_RSTN;
+	writel(val, base + CMN_PLL_POWER_ON_AND_RESET);
+	msleep(100);
+
+	return 0;
+}
+
+static int ipq_cmn_pll_clk_register(struct device *dev, const char *parent)
+{
+	const struct cmn_pll_fixed_clk *fixed_clk;
+	struct clk_hw_onecell_data *data;
+	const char *clk_name;
+	struct clk_hw *hw;
+	int index;
+
+	fixed_clk = of_device_get_match_data(dev);
+	if (!fixed_clk)
+		return -ENODEV;
+
+	data = devm_kzalloc(dev, struct_size(data, hws, fixed_clk->nrates),
+			    GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	/*
+	 * Register the fixed rate output clocks with the correct clock names,
+	 * the number of clocks and clock names are guaranteed by DTS.
+	 */
+	for (index = 0; index < fixed_clk->nrates; index++) {
+		if (of_property_read_string_index(dev->of_node,
+						  "clock-output-names",
+						  index, &clk_name))
+			return -ENODEV;
+
+		hw = devm_clk_hw_register_fixed_rate(dev, clk_name, parent, 0,
+						     fixed_clk->rates[index]);
+		if (IS_ERR(hw))
+			return PTR_ERR(hw);
+
+		data->hws[index] = hw;
+	}
+	data->num = fixed_clk->nrates;
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
+}
+
+static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct clk *clk;
+	int ret;
+
+	/*
+	 * To access the common PLL registers, the GCC AHB & SYSY clocks
+	 * for common PLL block need to be enabled.
+	 */
+	clk = devm_clk_get_enabled(dev, "ahb");
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Enable AHB clock failed\n");
+
+	clk = devm_clk_get_enabled(dev, "sys");
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Enable SYS clock failed\n");
+
+	clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Get reference clock failed\n");
+
+	/* Configure common PLL to apply the reference clock. */
+	ret = ipq_cmn_pll_config(dev, clk_get_rate(clk));
+	if (ret)
+		return dev_err_probe(dev, ret, "Configure common PLL failed\n");
+
+	return ipq_cmn_pll_clk_register(dev, __clk_get_name(clk));
+}
+
+static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
+	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_fixed_clk },
+	{ }
+};
+
+static struct platform_driver ipq_cmn_pll_clk_driver = {
+	.probe = ipq_cmn_pll_clk_probe,
+	.driver = {
+		.name = "ipq_cmn_pll",
+		.of_match_table = ipq_cmn_pll_clk_ids,
+	},
+};
+
+module_platform_driver(ipq_cmn_pll_clk_driver);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ Common PLL Driver");
+MODULE_LICENSE("GPL");