@@ -9,6 +9,7 @@
struct qmp_phy_init_tbl {
unsigned int offset;
unsigned int val;
+ char *name;
/*
* mask of lanes for which this register is written
* for cases when second lane needs different values
@@ -20,6 +21,7 @@ struct qmp_phy_init_tbl {
{ \
.offset = o, \
.val = v, \
+ .name = #o, \
.lane_mask = 0xff, \
}
@@ -27,6 +29,7 @@ struct qmp_phy_init_tbl {
{ \
.offset = o, \
.val = v, \
+ .name = #o, \
.lane_mask = l, \
}
@@ -45,6 +48,8 @@ static inline void qmp_configure_lane(void __iomem *base,
if (!(t->lane_mask & lane_mask))
continue;
+ pr_debug("QMP PHY: Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
+ t->name, t->offset, t->val);
writel(t->val, base + t->offset);
}
}
These register prints are useful to validate the init sequence against the Qcom internal documentation and also to share with the Qcom hw engineers to debug issues related to PHY. Sample debug prints: QMP PHY: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9 QMP PHY: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Changes in v2: * Modifed the debug print to include reg offset drivers/phy/qualcomm/phy-qcom-qmp-common.h | 5 +++++ 1 file changed, 5 insertions(+)