| Message ID | 20240719120853.1924771-3-m.majewski2@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add initial Exynos 850 support to the thermal driver | expand |
On Fri, Jul 19, 2024 at 7:10 AM Mateusz Majewski <m.majewski2@samsung.com> wrote: > > Some of the usages in sanitize_temp_error were missed, probably because > the boards being used never actually exceeded 255 in their trimming > information. This is needed for Exynos 850 support, which uses 9-bit > temperature codes. > That looks like an actual fix to me, so maybe also add the corresponding "Fixes:" tag here? > Signed-off-by: Mateusz Majewski <m.majewski2@samsung.com> > --- > drivers/thermal/samsung/exynos_tmu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c > index 9b7ca93a72f1..61606a9b9a00 100644 > --- a/drivers/thermal/samsung/exynos_tmu.c > +++ b/drivers/thermal/samsung/exynos_tmu.c > @@ -237,17 +237,17 @@ static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) > > data->temp_error1 = trim_info & tmu_temp_mask; > data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & EXYNOS_TRIMINFO_85_SHIFT=8 in the driver. Is that value actually correct in case of Exynos850? I just checked the TRM and it says the layout for TRIMINFO0 register is as follows: - RSVD: Bit [31:24] - CALIB_SEL: Bit [23] - T_BUF_VREF_SEL: Bit [22:18] - TRIMINFO_85_P0: Bit [17:9] - TRIMINFO_25_P0: Bit [8:0] So maybe that shift value should be 9 instead of 8 for Exynos850? Not sure about other platforms though, this might be also the case for Exynos7 SoCs too (SOC_ARCH_EXYNOS7 in the driver). > - EXYNOS_TMU_TEMP_MASK); > + tmu_temp_mask); > > if (!data->temp_error1 || > (data->min_efuse_value > data->temp_error1) || > (data->temp_error1 > data->max_efuse_value)) > - data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; > + data->temp_error1 = data->efuse_value & tmu_temp_mask; > > if (!data->temp_error2) > data->temp_error2 = > (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & > - EXYNOS_TMU_TEMP_MASK; > + tmu_temp_mask; > } > > static int exynos_tmu_initialize(struct platform_device *pdev) > -- > 2.45.1 > >
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 9b7ca93a72f1..61606a9b9a00 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -237,17 +237,17 @@ static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) data->temp_error1 = trim_info & tmu_temp_mask; data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & - EXYNOS_TMU_TEMP_MASK); + tmu_temp_mask); if (!data->temp_error1 || (data->min_efuse_value > data->temp_error1) || (data->temp_error1 > data->max_efuse_value)) - data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; + data->temp_error1 = data->efuse_value & tmu_temp_mask; if (!data->temp_error2) data->temp_error2 = (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & - EXYNOS_TMU_TEMP_MASK; + tmu_temp_mask; } static int exynos_tmu_initialize(struct platform_device *pdev)
Some of the usages in sanitize_temp_error were missed, probably because the boards being used never actually exceeded 255 in their trimming information. This is needed for Exynos 850 support, which uses 9-bit temperature codes. Signed-off-by: Mateusz Majewski <m.majewski2@samsung.com> --- drivers/thermal/samsung/exynos_tmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)