| Message ID | 20240718-sc7280-pcie-interrupts-v1-1-2047afa3b5b7@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: PCI: qcom,pcie-sc7280: specify eight interrupts | expand |
On Thu, Jul 18, 2024 at 04:20:34PM +0100, Rayyan Ansari wrote: > In the previous commit to this binding, > > commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") > > the binding was changed to specify one interrupt, as the device tree at > that moment in time did not describe the hardware fully. > > The device tree for sc7280 now specifies eight interrupts, due to > > commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrupts") > > As a result, change the bindings to reflect this. > > Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 24 ++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > index 634da24ec3ed..5cf1f9165301 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > @@ -53,11 +53,19 @@ properties: > - const: aggre1 # Aggre NoC PCIe1 AXI clock > > interrupts: > - maxItems: 1 > + minItems: 8 > + maxItems: 8 > > interrupt-names: > items: > - - const: msi > + - const: msi0 > + - const: msi1 > + - const: msi2 > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > > resets: > maxItems: 1 > @@ -137,8 +145,16 @@ examples: > > dma-coherent; > > - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi"; > + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi0", "msi1", "msi2", "msi3", > + "msi4", "msi5", "msi6", "msi7"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, > > --- > base-commit: 73399b58e5e5a1b28a04baf42e321cfcfc663c2f > change-id: 20240718-sc7280-pcie-interrupts-6d34650d9bb2 > > Best regards, > -- > Rayyan Ansari <rayyan.ansari@linaro.org> >
On 18/07/2024 17:20, Rayyan Ansari wrote: > In the previous commit to this binding, > > commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") "commit foo ("bar")" is always part of the sentence, so drop surrounding blank lines. > > the binding was changed to specify one interrupt, as the device tree at > that moment in time did not describe the hardware fully. > > The device tree for sc7280 now specifies eight interrupts, due to > > commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrupts") Same here. > > As a result, change the bindings to reflect this. > > Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 24 ++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > With above: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 634da24ec3ed..5cf1f9165301 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -53,11 +53,19 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - maxItems: 1 + minItems: 8 + maxItems: 8 interrupt-names: items: - - const: msi + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 resets: maxItems: 1 @@ -137,8 +145,16 @@ examples: dma-coherent; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
In the previous commit to this binding, commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") the binding was changed to specify one interrupt, as the device tree at that moment in time did not describe the hardware fully. The device tree for sc7280 now specifies eight interrupts, due to commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrupts") As a result, change the bindings to reflect this. Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 24 ++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) --- base-commit: 73399b58e5e5a1b28a04baf42e321cfcfc663c2f change-id: 20240718-sc7280-pcie-interrupts-6d34650d9bb2 Best regards,