| Message ID | 20240711090250.20827-1-johan+linaro@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe | expand |
On Thu, Jul 11, 2024 at 06:59:22PM +0200, Johan Hovold wrote: > On Thu, Jul 11, 2024 at 10:11:53PM +0530, Manivannan Sadhasivam wrote: > > On Thu, Jul 11, 2024 at 09:49:52PM +0530, Manivannan Sadhasivam wrote: > > > My hunch is the PHY settings. But Abel cross checked the PHY settings with > > > internal documentation and they seem to match. Also, Qcom submitted a series > > > that is supposed to fix stability issues with Gen4 [1]. With this series, Gen 4 > > > x4 setup is working on SA8775P-RIDE board as reported by Qcom. But Abel > > > confirmed that it didn't help him with the link downgrade issue. > > > > > > Perhaps you can give it a try and see if it makes any difference for > > > this issue? > > If there are known issues with running at Gen4 speed without that > series, then it seems quite likely that doing so anyway could also cause > correctable errors. > > Unfortunately, I get a hypervisor reset when I tried booting with that > series so there appears to be some implicit dependency on something > else (e.g. the 4l stuff). The first patch in that series breaks icc handling, which crashes machines like the X13s and the x1e80100 CRD on boot. I've just reported this here: https://lore.kernel.org/lkml/ZpDlf5xD035x2DqL@hovoldconsulting.com/ With that fixed, and with the hacky dependency on having max-link-speed specified in the DT for the series to have any affect at all, the gen4 stability series indeed seems to make the AER error go away (Abel just confirmed using a branch I'd prepared). Let's try to get that series in shape and merged in some form as everyone will be hitting these Correctable Errors currently with the NVMe on x1e80100. Johan
On Fri, Jul 12, 2024 at 10:20:24AM +0200, Johan Hovold wrote: > On Thu, Jul 11, 2024 at 06:59:22PM +0200, Johan Hovold wrote: > > On Thu, Jul 11, 2024 at 10:11:53PM +0530, Manivannan Sadhasivam wrote: > > > On Thu, Jul 11, 2024 at 09:49:52PM +0530, Manivannan Sadhasivam wrote: > > > > > My hunch is the PHY settings. But Abel cross checked the PHY settings with > > > > internal documentation and they seem to match. Also, Qcom submitted a series > > > > that is supposed to fix stability issues with Gen4 [1]. With this series, Gen 4 > > > > x4 setup is working on SA8775P-RIDE board as reported by Qcom. But Abel > > > > confirmed that it didn't help him with the link downgrade issue. > > > > > > > > Perhaps you can give it a try and see if it makes any difference for > > > > this issue? > > > > If there are known issues with running at Gen4 speed without that > > series, then it seems quite likely that doing so anyway could also cause > > correctable errors. > > > > Unfortunately, I get a hypervisor reset when I tried booting with that > > series so there appears to be some implicit dependency on something > > else (e.g. the 4l stuff). > > The first patch in that series breaks icc handling, which crashes > machines like the X13s and the x1e80100 CRD on boot. I've just reported > this here: > > https://lore.kernel.org/lkml/ZpDlf5xD035x2DqL@hovoldconsulting.com/ > Ah, what a blinder... Thanks for reporting. But I'm wondering why Abel was not seeing this crash when he tested this series for 4L. > With that fixed, and with the hacky dependency on having max-link-speed > specified in the DT for the series to have any affect at all, the gen4 > stability series indeed seems to make the AER error go away (Abel just > confirmed using a branch I'd prepared). > Cool, good to know. > Let's try to get that series in shape and merged in some form as > everyone will be hitting these Correctable Errors currently with the > NVMe on x1e80100. > Sure. This series anyway needs respin due to the dependency with the OPP series that just got merged. But merging it for 6.11 is quite unlikely. - Mani
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 32a73ff672be..5822ed97ad87 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3114,6 +3114,8 @@ pcie6a: pci@1bf8000 { linux,pci-domain = <7>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, @@ -3235,6 +3237,8 @@ pcie4: pci@1c08000 { linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -5394,8 +5398,6 @@ gic_its: msi-controller@17040000 { msi-controller; #msi-cells = <1>; - - status = "disabled"; }; };
The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)