| Message ID | 20240709-add_qcs9100_pcie_phy_compatible-v2-2-c68f1e38560b@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | phy: qcom-qmp-pcie: Add QCS9100 x4 lane EP compatible | expand |
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 5b36cc7ac78b..d462b21706ee 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4339,6 +4339,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,msm8998-qmp-pcie-phy", .data = &msm8998_pciephy_cfg, + }, { + .compatible = "qcom,qcs9100-qmp-gen4x2-pcie-phy", + .data = &sa8775p_qmp_gen4x2_pciephy_cfg, + }, { + .compatible = "qcom,qcs9100-qmp-gen4x4-pcie-phy", + .data = &sa8775p_qmp_gen4x4_pciephy_cfg, }, { .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", .data = &sa8775p_qmp_gen4x2_pciephy_cfg,
Add support for x4 lane end point mode PHY found on QCS9100 platform. Reusing existing serdes and pcs_misc table for EP and moved BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes table as this register is part of both RC and EP. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-qmp-gen4x2-pcie-phy" and "qcom,qcs9100-qmp-gen4x4-pcie-phy" to the qmp pcie device match table. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ++++++ 1 file changed, 6 insertions(+)