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[v2,30/60] i2c: mpc: reword according to newest specification

Message ID 20240706112116.24543-31-wsa+renesas@sang-engineering.com
State New
Headers show
Series i2c: reword first drivers according to newest specification | expand

Commit Message

Wolfram Sang July 6, 2024, 11:20 a.m. UTC
Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2
specifications and replace "master/slave" with more appropriate terms.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/i2c/busses/i2c-mpc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Chris Packham July 7, 2024, 8:52 p.m. UTC | #1
On 6/07/24 23:20, Wolfram Sang wrote:
> Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2
> specifications and replace "master/slave" with more appropriate terms.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>   drivers/i2c/busses/i2c-mpc.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
> index c4223556b3b8..41d6c8ed163a 100644
> --- a/drivers/i2c/busses/i2c-mpc.c
> +++ b/drivers/i2c/busses/i2c-mpc.c
> @@ -115,7 +115,7 @@ static inline void writeccr(struct mpc_i2c *i2c, u32 x)
>   	writeb(x, i2c->base + MPC_I2C_CR);
>   }
>   
> -/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
> +/* Sometimes 9th clock pulse isn't generated, and target doesn't release
>    * the bus, because it wants to send ACK.
>    * Following sequence of enabling/disabling and sending start/stop generates
>    * the 9 pulses, each with a START then ending with STOP, so it's all OK.
> @@ -759,7 +759,7 @@ static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
>   }
>   
>   static const struct i2c_algorithm mpc_algo = {
> -	.master_xfer = mpc_xfer,
> +	.xfer = mpc_xfer,
>   	.functionality = mpc_functionality,
>   };
>
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Patch

diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index c4223556b3b8..41d6c8ed163a 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -115,7 +115,7 @@  static inline void writeccr(struct mpc_i2c *i2c, u32 x)
 	writeb(x, i2c->base + MPC_I2C_CR);
 }
 
-/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
+/* Sometimes 9th clock pulse isn't generated, and target doesn't release
  * the bus, because it wants to send ACK.
  * Following sequence of enabling/disabling and sending start/stop generates
  * the 9 pulses, each with a START then ending with STOP, so it's all OK.
@@ -759,7 +759,7 @@  static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
 }
 
 static const struct i2c_algorithm mpc_algo = {
-	.master_xfer = mpc_xfer,
+	.xfer = mpc_xfer,
 	.functionality = mpc_functionality,
 };