diff mbox

[v3,1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum

Message ID 1478264794-14652-1-git-send-email-dingtianhong@huawei.com
State Superseded
Headers show

Commit Message

Ding Tianhong Nov. 4, 2016, 1:06 p.m. UTC
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

v2: Use the new erratum name and update the description.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>

Acked-by: Rob Herring <robh@kernel.org>

---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

-- 
1.9.0


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Comments

Scott Wood Nov. 4, 2016, 6:20 p.m. UTC | #1
On Fri, Nov 04, 2016 at 09:06:30PM +0800, Ding Tianhong wrote:
> The workaround for hisilicon,161601 will check the return value of the system counter

> by different way, in order to distinguish with the fsl-a008585 workaround, introduce

> a new generic erratum handing mechanism for fsl-a008585 and rename some functions.

> 

> v2: Introducing a new generic erratum handling mechanism for fsl erratum a008585.

> 

> v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585

>     and make the #define __fsl_a008585_read_reg to be private to the .c file instead of

>     being globally visible. After discussion with Marc and Will, a consensus decision was

>     made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,

>     and make some generic name more specific, export timer_unstable_counter_workaround

>     for module access.


The command line paramter was added at Marc's request to provide a way of
enbaling the workaround in a KVM guest, until API is added to allow QEMU to
discover the need to set the property in the guest device tree.  Is there an
alternative?

-Scott
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Will Deacon Nov. 4, 2016, 6:55 p.m. UTC | #2
On Fri, Nov 04, 2016 at 01:20:50PM -0500, Scott Wood wrote:
> On Fri, Nov 04, 2016 at 09:06:30PM +0800, Ding Tianhong wrote:

> > The workaround for hisilicon,161601 will check the return value of the system counter

> > by different way, in order to distinguish with the fsl-a008585 workaround, introduce

> > a new generic erratum handing mechanism for fsl-a008585 and rename some functions.

> > 

> > v2: Introducing a new generic erratum handling mechanism for fsl erratum a008585.

> > 

> > v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585

> >     and make the #define __fsl_a008585_read_reg to be private to the .c file instead of

> >     being globally visible. After discussion with Marc and Will, a consensus decision was

> >     made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum,

> >     and make some generic name more specific, export timer_unstable_counter_workaround

> >     for module access.

> 

> The command line paramter was added at Marc's request to provide a way of

> enbaling the workaround in a KVM guest, until API is added to allow QEMU to

> discover the need to set the property in the guest device tree.  Is there an

> alternative?


Yes -- generate the device-tree property to indicate that there's an issue.

Will
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ef5fbe9..c27b2c4 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@  to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161601 : A boolean property. Indicates the presence of
+  erratum 161601, which says that reading the counter is unreliable unless
+  reading twice on the register and the value of the second read is larger
+  than the first by less than 32. If the verification is unsuccessful, then
+  discard the value of this read and repeat this procedure until the verification
+  is successful.  This also affects writes to the tval register, due to the
+  implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize