diff mbox series

[v4,1/3] dt-bindings: mmc: renesas,sdhi: Document RZ/V2H(P) support

Message ID 20240626132341.342963-2-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series Add SD/MMC support for Renesas RZ/V2H(P) SoC | expand

Commit Message

Lad, Prabhakar June 26, 2024, 1:23 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that
of the R-Car Gen3, but it has some differences:
- HS400 is not supported.
- It supports the SD_IOVS bit to control the IO voltage level.
- It supports fixed address mode.

To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057'
compatible string is added.

A 'vqmmc-regulator' object is introduced to handle the power enable (PWEN)
and voltage level switching for the SD/MMC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- Dropped 'renesas,sdhi-use-internal-regulator' property
- Moved 'vqmmc-regulator' to the top level

v2->v3
- Renamed vqmmc-r9a09g057-regulator object to vqmmc-regulator
- Added regulator-compatible property for vqmmc-regulator
- Added 'renesas,sdhi-use-internal-regulator' property

v1->v2
- Moved vqmmc object in the if block
- Updated commit message
---
 .../devicetree/bindings/mmc/renesas,sdhi.yaml | 26 ++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

Comments

Wolfram Sang July 3, 2024, 9:38 a.m. UTC | #1 
On Wed, Jun 26, 2024 at 02:23:39PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that
> of the R-Car Gen3, but it has some differences:
> - HS400 is not supported.
> - It supports the SD_IOVS bit to control the IO voltage level.
> - It supports fixed address mode.
> 
> To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057'
> compatible string is added.
> 
> A 'vqmmc-regulator' object is introduced to handle the power enable (PWEN)
> and voltage level switching for the SD/MMC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Can we have an example here? I can read DTS snippets better than YAML
code :/ Also wondering about the "regulator-compatible" property but
maybe the example makes the problem clear?
Lad, Prabhakar July 4, 2024, 6:27 p.m. UTC | #2 
Hi Wolfram,

On Wed, Jul 3, 2024 at 10:38 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> On Wed, Jun 26, 2024 at 02:23:39PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that
> > of the R-Car Gen3, but it has some differences:
> > - HS400 is not supported.
> > - It supports the SD_IOVS bit to control the IO voltage level.
> > - It supports fixed address mode.
> >
> > To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057'
> > compatible string is added.
> >
> > A 'vqmmc-regulator' object is introduced to handle the power enable (PWEN)
> > and voltage level switching for the SD/MMC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Can we have an example here? I can read DTS snippets better than YAML
> code :/ Also wondering about the "regulator-compatible" property but
> maybe the example makes the problem clear?
>
You mean in the commit message or comment section? (I had added below
in the cover letter)

SoC DTSI node:
sdhi1: mmc@15c10000 {
        compatible = "renesas,sdhi-r9a09g057";
        reg = <0x0 0x15c10000 0 0x10000>;
        interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 167>,
                        <&cpg CPG_MOD 169>,
                        <&cpg CPG_MOD 168>,
                        <&cpg CPG_MOD 170>;
        clock-names = "core", "clkh", "cd", "aclk";
        resets = <&cpg 168>;
        power-domains = <&cpg>;
        status = "disabled";

        vqmmc_sdhi1: vqmmc-regulator {
                regulator-compatible = "vqmmc-r9a09g057-regulator";
                regulator-name = "sdhi1-vqmmc-regulator";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <3300000>;
                status = "disabled";
        };
};

Board DTS:
&sdhi1 {
        pinctrl-0 = <&sdhi1_pins>;
        pinctrl-1 = <&sdhi1_pins>;
        pinctrl-names = "default", "state_uhs";
        vmmc-supply = <&reg_3p3v>;
        vqmmc-supply = <&vqmmc_sdhi1>;
        bus-width = <4>;
        sd-uhs-sdr50;
        sd-uhs-sdr104;
        status = "okay";
};

&vqmmc_sdhi1 {
     status = "okay";
};

Based on feedback from Conor, we cannot use the regulator-compatible
property. This would require us to implement separate drivers (one for
VMMC and another for VQMMC), which I believe would necessitate the use
of regmap. Currently, this seems unnecessary for controlling the two
bits as a regulator. As Geert previously pointed out, the PWEN and
IOVS pins can always be multiplexed as GPIOs on the RZ/V2H SoC (as is
done on R-Car devices). Therefore, I am inclined to drop the internal
regulator support for now.

Let me know your thoughts.

Cheers,
Prabhakar
Lad, Prabhakar July 22, 2024, 1:19 p.m. UTC | #3 
Hi Wolfram,

On Thu, Jul 4, 2024 at 7:27 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Wolfram,
>
> On Wed, Jul 3, 2024 at 10:38 AM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> >
> > On Wed, Jun 26, 2024 at 02:23:39PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that
> > > of the R-Car Gen3, but it has some differences:
> > > - HS400 is not supported.
> > > - It supports the SD_IOVS bit to control the IO voltage level.
> > > - It supports fixed address mode.
> > >
> > > To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057'
> > > compatible string is added.
> > >
> > > A 'vqmmc-regulator' object is introduced to handle the power enable (PWEN)
> > > and voltage level switching for the SD/MMC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Can we have an example here? I can read DTS snippets better than YAML
> > code :/ Also wondering about the "regulator-compatible" property but
> > maybe the example makes the problem clear?
> >
> You mean in the commit message or comment section? (I had added below
> in the cover letter)
>
> SoC DTSI node:
> sdhi1: mmc@15c10000 {
>         compatible = "renesas,sdhi-r9a09g057";
>         reg = <0x0 0x15c10000 0 0x10000>;
>         interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
>                         <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
>         clocks = <&cpg CPG_MOD 167>,
>                         <&cpg CPG_MOD 169>,
>                         <&cpg CPG_MOD 168>,
>                         <&cpg CPG_MOD 170>;
>         clock-names = "core", "clkh", "cd", "aclk";
>         resets = <&cpg 168>;
>         power-domains = <&cpg>;
>         status = "disabled";
>
>         vqmmc_sdhi1: vqmmc-regulator {
>                 regulator-compatible = "vqmmc-r9a09g057-regulator";
>                 regulator-name = "sdhi1-vqmmc-regulator";
>                 regulator-min-microvolt = <1800000>;
>                 regulator-max-microvolt = <3300000>;
>                 status = "disabled";
>         };
> };
>
> Board DTS:
> &sdhi1 {
>         pinctrl-0 = <&sdhi1_pins>;
>         pinctrl-1 = <&sdhi1_pins>;
>         pinctrl-names = "default", "state_uhs";
>         vmmc-supply = <&reg_3p3v>;
>         vqmmc-supply = <&vqmmc_sdhi1>;
>         bus-width = <4>;
>         sd-uhs-sdr50;
>         sd-uhs-sdr104;
>         status = "okay";
> };
>
> &vqmmc_sdhi1 {
>      status = "okay";
> };
>
> Based on feedback from Conor, we cannot use the regulator-compatible
> property. This would require us to implement separate drivers (one for
> VMMC and another for VQMMC), which I believe would necessitate the use
> of regmap. Currently, this seems unnecessary for controlling the two
> bits as a regulator. As Geert previously pointed out, the PWEN and
> IOVS pins can always be multiplexed as GPIOs on the RZ/V2H SoC (as is
> done on R-Car devices). Therefore, I am inclined to drop the internal
> regulator support for now.
>
> Let me know your thoughts.
>
Gentle ping.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 3d0e61e59856..d632b67080bd 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -18,6 +18,7 @@  properties:
           - renesas,sdhi-r7s9210 # SH-Mobile AG5
           - renesas,sdhi-r8a73a4 # R-Mobile APE6
           - renesas,sdhi-r8a7740 # R-Mobile A1
+          - renesas,sdhi-r9a09g057 # RZ/V2H(P)
           - renesas,sdhi-sh73a0  # R-Mobile APE6
       - items:
           - enum:
@@ -111,6 +112,15 @@  properties:
 
   max-frequency: true
 
+  vqmmc-regulator:
+    type: object
+    description: VQMMC SD regulator
+    $ref: /schemas/regulator/regulator.yaml#
+    unevaluatedProperties: false
+    properties:
+      regulator-compatible:
+        pattern: "^vqmmc-r9a09g057-regulator"
+
 allOf:
   - $ref: mmc-controller.yaml
 
@@ -118,7 +128,9 @@  allOf:
       properties:
         compatible:
           contains:
-            const: renesas,rzg2l-sdhi
+            enum:
+              - renesas,sdhi-r9a09g057
+              - renesas,rzg2l-sdhi
     then:
       properties:
         clocks:
@@ -204,6 +216,18 @@  allOf:
         sectioned off to be run by a separate second clock source to allow
         the main core clock to be turned off to save power.
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,sdhi-r9a09g057
+    then:
+      required:
+        - vqmmc-regulator
+    else:
+      properties:
+        vqmmc-regulator: false
+
 required:
   - compatible
   - reg