Message ID | 20240618160039.36108-55-philmd@linaro.org |
---|---|
State | New |
Headers | show
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Tue, 18 Jun 2024 09:05:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell <peter.maydell@linaro.org>, =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= <philmd@linaro.org>, Richard Henderson <richard.henderson@linaro.org> Subject: [PULL 54/76] target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() Date: Tue, 18 Jun 2024 18:00:16 +0200 Message-ID: <20240618160039.36108-55-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240618160039.36108-1-philmd@linaro.org> References: <20240618160039.36108-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
[PULL,01/76] hw/i386/pc: Deprecate 2.4 to 2.12 pc-i440fx machines
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diff --git a/target/arm/internals.h b/target/arm/internals.h index 11b5da2562..e45ccd983e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -364,6 +364,9 @@ void arm_restore_state_to_opc(CPUState *cs, #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); + +/* Our implementation of TCGCPUOps::cpu_exec_halt */ +bool arm_cpu_exec_halt(CPUState *cs); #endif /* CONFIG_TCG */ typedef enum ARMFPRounding { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 35fa281f1b..948e904bd8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1133,7 +1133,7 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) } #ifdef CONFIG_TCG -static bool arm_cpu_exec_halt(CPUState *cs) +bool arm_cpu_exec_halt(CPUState *cs) { bool leave_halt = cpu_has_work(cs); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c059c681e9..5496f14dc1 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -244,6 +244,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = { #else .tlb_fill = arm_cpu_tlb_fill, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, + .cpu_exec_halt = arm_cpu_exec_halt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access,