| Message ID | 20240606125755.53778-3-i@eh5.me |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: rockchip: fix RK3328 pinmux bits | expand |
Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao: > The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly > specified in RK3328 TRM, however we can get hint from pad name and its > correspinding IOMUX setting for pins in interface descriptions. The > correspinding IOMIX settings for these pins can be found in the same > row next to occurrences of following pad names in RK3328 TRM. > > GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 > GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 > GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 > GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 > GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 > GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 > > Add pinmux data to rk3328_mux_recalced_data as mux register offset for > these pins does not follow rockchip convention. > > Signed-off-by: Huang-Huang Bao <i@eh5.me> This matches the information that I found in my TRM, thanks to your detailed explanation. Though I of course can't say if the TRM is just wrong or the hardware changed after the pads-description was written. Did you test the usage of these pins on your board? Heiko > --- > drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c > index 78dcf4daccde..23531ea0d088 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { > > static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { > { > + /* gpio2_b7_sel */ > .num = 2, > .pin = 15, > .reg = 0x28, > .bit = 0, > .mask = 0x7 > }, { > + /* gpio2_c7_sel */ > .num = 2, > .pin = 23, > .reg = 0x30, > .bit = 14, > .mask = 0x3 > + }, { > + /* gpio3_b1_sel */ > + .num = 3, > + .pin = 9, > + .reg = 0x44, > + .bit = 2, > + .mask = 0x3 > + }, { > + /* gpio3_b2_sel */ > + .num = 3, > + .pin = 10, > + .reg = 0x44, > + .bit = 4, > + .mask = 0x3 > + }, { > + /* gpio3_b3_sel */ > + .num = 3, > + .pin = 11, > + .reg = 0x44, > + .bit = 6, > + .mask = 0x3 > + }, { > + /* gpio3_b4_sel */ > + .num = 3, > + .pin = 12, > + .reg = 0x44, > + .bit = 8, > + .mask = 0x3 > + }, { > + /* gpio3_b5_sel */ > + .num = 3, > + .pin = 13, > + .reg = 0x44, > + .bit = 10, > + .mask = 0x3 > + }, { > + /* gpio3_b6_sel */ > + .num = 3, > + .pin = 14, > + .reg = 0x44, > + .bit = 12, > + .mask = 0x3 > + }, { > + /* gpio3_b7_sel */ > + .num = 3, > + .pin = 15, > + .reg = 0x44, > + .bit = 14, > + .mask = 0x3 > }, > }; > >
On 6/6/24 20:57, Huang-Huang Bao wrote: > The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly > specified in RK3328 TRM, however we can get hint from pad name and its > correspinding IOMUX setting for pins in interface descriptions. The > correspinding IOMIX settings for these pins can be found in the same > row next to occurrences of following pad names in RK3328 TRM. > > GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 > GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 > GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 > GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 > GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 > GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 > > Add pinmux data to rk3328_mux_recalced_data as mux register offset for > these pins does not follow rockchip convention. > > Signed-off-by: Huang-Huang Bao <i@eh5.me> This is also Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 78dcf4daccde..23531ea0d088 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, };
The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for these pins can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 Add pinmux data to rk3328_mux_recalced_data as mux register offset for these pins does not follow rockchip convention. Signed-off-by: Huang-Huang Bao <i@eh5.me> --- drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)