| Message ID | 20240531120401.394550-1-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 5/31/24 05:03, Peter Maydell wrote: > The following changes since commit 3b2fe44bb7f605f179e5e7feb2c13c2eb3abbb80: > > Merge tag 'pull-request-2024-05-29' ofhttps://gitlab.com/thuth/qemu into staging (2024-05-29 08:38:20 -0700) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240531 > > for you to fetch changes up to 3c3c233677d4f2fe5f35c5d6d6e9b53df48054f4: > > hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT (2024-05-31 11:26:00 +0100) > > ---------------------------------------------------------------- > target-arm: > * hw/intc/arm_gic: Fix set pending of PPIs > * hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn > * xilinx_zynq: Add cache controller > * xilinx_zynq: Support up to two CPU cores > * tests/avocado: update sbsa-ref firmware > * sbsa-ref: move to Neoverse-N2 as default > * More decodetree conversion of A64 ASIMD insns > * docs/system/target-arm: Re-alphabetize board list > * Implement FEAT WFxT and enable for '-cpu max' > * hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
The following changes since commit 3b2fe44bb7f605f179e5e7feb2c13c2eb3abbb80: Merge tag 'pull-request-2024-05-29' of https://gitlab.com/thuth/qemu into staging (2024-05-29 08:38:20 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240531 for you to fetch changes up to 3c3c233677d4f2fe5f35c5d6d6e9b53df48054f4: hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT (2024-05-31 11:26:00 +0100) ---------------------------------------------------------------- target-arm: * hw/intc/arm_gic: Fix set pending of PPIs * hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn * xilinx_zynq: Add cache controller * xilinx_zynq: Support up to two CPU cores * tests/avocado: update sbsa-ref firmware * sbsa-ref: move to Neoverse-N2 as default * More decodetree conversion of A64 ASIMD insns * docs/system/target-arm: Re-alphabetize board list * Implement FEAT WFxT and enable for '-cpu max' * hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT ---------------------------------------------------------------- David Hubbard (1): hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT Marcin Juszkiewicz (3): tests/avocado: update sbsa-ref firmware arm/sbsa-ref: move to Neoverse-N2 as default target/arm: Disable SVE extensions when SVE is disabled Peter Maydell (3): docs/system/target-arm: Re-alphabetize board list accel/tcg: Make TCGCPUOps::cpu_exec_halt return bool for whether to halt target/arm: Implement FEAT WFxT and enable for '-cpu max' Richard Henderson (32): target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB target/arm: Assert oprsz in range when using vfp.qc target/arm: Convert SUQADD and USQADD to gvec target/arm: Inline scalar SUQADD and USQADD target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree target/arm: Convert SUQADD, USQADD to decodetree target/arm: Convert SSHL, USHL to decodetree target/arm: Convert SRSHL and URSHL (register) to gvec target/arm: Convert SRSHL, URSHL to decodetree target/arm: Convert SQSHL and UQSHL (register) to gvec target/arm: Convert SQSHL, UQSHL to decodetree target/arm: Convert SQRSHL and UQRSHL (register) to gvec target/arm: Convert SQRSHL, UQRSHL to decodetree target/arm: Convert ADD, SUB (vector) to decodetree target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64} target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec target/arm: Convert SHADD, UHADD to gvec target/arm: Convert SHADD, UHADD to decodetree target/arm: Convert SHSUB, UHSUB to gvec target/arm: Convert SHSUB, UHSUB to decodetree target/arm: Convert SRHADD, URHADD to gvec target/arm: Convert SRHADD, URHADD to decodetree target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree target/arm: Convert SABA, SABD, UABA, UABD to decodetree target/arm: Convert MUL, PMUL to decodetree target/arm: Convert MLA, MLS to decodetree target/arm: Tidy SQDMULH, SQRDMULH (vector) target/arm: Convert SQDMULH, SQRDMULH to decodetree target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree target/arm: Convert FCSEL to decodetree Sebastian Huber (4): hw/intc/arm_gic: Fix set pending of PPIs hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn hw/arm/xilinx_zynq: Add cache controller hw/arm/xilinx_zynq: Support up to two CPU cores docs/system/arm/emulation.rst | 1 + docs/system/target-arm.rst | 6 +- include/hw/core/tcg-cpu-ops.h | 15 +- target/arm/cpu-features.h | 5 + target/arm/cpu.h | 3 + target/arm/helper.h | 97 ++- target/arm/internals.h | 8 + target/arm/tcg/translate-a64.h | 14 + target/arm/tcg/translate.h | 44 + target/i386/tcg/helper-tcg.h | 2 +- target/arm/tcg/a64.decode | 119 +++ target/arm/tcg/neon-dp.decode | 37 +- accel/tcg/cpu-exec.c | 7 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/xilinx_zynq.c | 55 +- hw/intc/arm_gic.c | 12 +- hw/usb/hcd-ohci.c | 5 + target/arm/cpu.c | 40 + target/arm/cpu64.c | 6 +- target/arm/helper.c | 4 +- target/arm/machine.c | 20 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/gengvec.c | 689 ++++++++++++++- target/arm/tcg/gengvec64.c | 181 ++++ target/arm/tcg/neon_helper.c | 506 +++-------- target/arm/tcg/op_helper.c | 54 ++ target/arm/tcg/translate-a64.c | 1362 +++++++++++------------------- target/arm/tcg/translate-neon.c | 118 +-- target/arm/tcg/vec_helper.c | 128 +++ target/i386/tcg/sysemu/seg_helper.c | 3 +- hw/arm/Kconfig | 1 + hw/usb/trace-events | 1 + tests/avocado/machine_aarch64_sbsaref.py | 20 +- 33 files changed, 2034 insertions(+), 1532 deletions(-)