@@ -24,7 +24,9 @@
&empty !extern
&i !extern imm
+&r !extern rm
&setend E
+&nm rn rm
# Branch with Link and Exchange
@@ -61,9 +63,9 @@ PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te
PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp
PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7
-PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te
-PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp
-PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7
+PLD_rr 1111 0111 -101 ---- 1111 ----- -- 0 rm:4 &r
+PLDW_rr 1111 0111 -001 rn:4 1111 ----- -- 0 rm:4 &nm
+PLI_rr 1111 0110 -101 ---- 1111 ----- -- 0 rm:4 &r
# Unallocated memory hints
#
@@ -28,6 +28,7 @@
&rrr_rot !extern rd rn rm rot
&rrr !extern rd rn rm
&rr !extern rd rm
+&nm !extern rn rm
&ri !extern rd imm
&r !extern rm
&i !extern imm
@@ -472,7 +473,7 @@ STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos
}
LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp
{
- PLD 1111 1000 0001 ---- 1111 000000 -- ---- # (register)
+ PLD_rr 1111 1000 0001 ---- 1111 000000 -- rm:4 &r
LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr
}
}
@@ -492,7 +493,7 @@ STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos
}
LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp
{
- PLDW 1111 1000 0011 ---- 1111 000000 -- ---- # (register)
+ PLDW_rr 1111 1000 0011 rn:4 1111 000000 -- rm:4 &nm
LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr
}
}
@@ -520,7 +521,7 @@ STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos
}
LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp
{
- PLI 1111 1001 0001 ---- 1111 000000 -- ---- # (register)
+ PLI_rr 1111 1001 0001 ---- 1111 000000 -- rm:4 &r
LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr
}
}
@@ -7187,6 +7187,64 @@ static bool trans_PLI(DisasContext *s, arg_PLI *a)
return ENABLE_ARCH_7;
}
+/* Check for UNPREDICTABLE rm for prefetch (register). */
+static bool prefetch_check_m(DisasContext *s, int rm)
+{
+ switch (rm) {
+ case 13:
+ /* SP allowed in v8 or with A1 encoding; rejected with T1. */
+ return ENABLE_ARCH_8 || !s->thumb;
+ case 15:
+ /* PC always rejected. */
+ return false;
+ default:
+ return true;
+ }
+}
+
+static bool trans_PLD_rr(DisasContext *s, arg_PLD_rr *a)
+{
+ if (!ENABLE_ARCH_5TE) {
+ return false;
+ }
+ /* Choose UNDEF for UNPREDICTABLE rm. */
+ if (!prefetch_check_m(s, a->rm)) {
+ unallocated_encoding(s);
+ }
+ return true;
+}
+
+static bool trans_PLDW_rr(DisasContext *s, arg_PLDW_rr *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
+ return false;
+ }
+ /*
+ * For A1, rn == 15 is UNPREDICTABLE.
+ * For T1, rn == 15 is PLD (literal), and already matched.
+ * Choose UNDEF for UNPREDICTABLE rn or rm.
+ */
+ if (a->rn == 15) {
+ assert(!s->thumb);
+ } else if (prefetch_check_m(s, a->rm)) {
+ return true;
+ }
+ unallocated_encoding(s);
+ return true;
+}
+
+static bool trans_PLI_rr(DisasContext *s, arg_PLI_rr *a)
+{
+ if (!ENABLE_ARCH_7) {
+ return false;
+ }
+ /* Choose UNDEF for UNPREDICTABLE rm. */
+ if (!prefetch_check_m(s, a->rm)) {
+ unallocated_encoding(s);
+ }
+ return true;
+}
+
/*
* If-then
*/
For all, rm == 15 is UNPREDICTABLE. Prior to v8, thumb with rm == 13 is UNPREDICTABLE. For PLDW, rn == 15 is UNPREDICTABLE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/a32-uncond.decode | 8 +++-- target/arm/tcg/t32.decode | 7 ++-- target/arm/tcg/translate.c | 58 ++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 6 deletions(-)