[v3,25/33] target/arm: Convert SRHADD, URHADD to decodetree

Message ID	20240528203044.612851-26-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org> Subject: [PATCH v3 25/33] target/arm: Convert SRHADD, URHADD to decodetree Date: Tue, 28 May 2024 13:30:36 -0700 Message-Id: <20240528203044.612851-26-richard.henderson@linaro.org> In-Reply-To: <20240528203044.612851-1-richard.henderson@linaro.org> References: <20240528203044.612851-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Convert a64 advsimd to decodetree (part 1b) \| expand [v3,00/33] target/arm: Convert a64 advsimd to decodetree (part 1b) [v3,01/33] target/arm: Diagnose UNPREDICTABLE operands to PLD, PLDW, PLI [v3,02/33] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB [v3,03/33] target/arm: Assert oprsz in range when using vfp.qc [v3,04/33] target/arm: Convert SUQADD and USQADD to gvec [v3,05/33] target/arm: Inline scalar SUQADD and USQADD [v3,06/33] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB [v3,07/33] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree [v3,08/33] target/arm: Convert SUQADD, USQADD to decodetree [v3,09/33] target/arm: Convert SSHL, USHL to decodetree [v3,10/33] target/arm: Convert SRSHL and URSHL (register) to gvec [v3,11/33] target/arm: Convert SRSHL, URSHL to decodetree [v3,12/33] target/arm: Convert SQSHL and UQSHL (register) to gvec [v3,13/33] target/arm: Convert SQSHL, UQSHL to decodetree [v3,14/33] target/arm: Convert SQRSHL and UQRSHL (register) to gvec [v3,15/33] target/arm: Convert SQRSHL, UQRSHL to decodetree [v3,16/33] target/arm: Convert ADD, SUB (vector) to decodetree [v3,17/33] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree [v3,18/33] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64} [v3,19/33] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec [v3,20/33] target/arm: Convert SHADD, UHADD to gvec [v3,21/33] target/arm: Convert SHADD, UHADD to decodetree [v3,22/33] target/arm: Convert SHSUB, UHSUB to gvec [v3,23/33] target/arm: Convert SHSUB, UHSUB to decodetree [v3,24/33] target/arm: Convert SRHADD, URHADD to gvec [v3,25/33] target/arm: Convert SRHADD, URHADD to decodetree [v3,26/33] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree [v3,27/33] target/arm: Convert SABA, SABD, UABA, UABD to decodetree [v3,28/33] target/arm: Convert MUL, PMUL to decodetree [v3,29/33] target/arm: Convert MLA, MLS to decodetree [v3,30/33] target/arm: Tidy SQDMULH, SQRDMULH (vector) [v3,31/33] target/arm: Convert SQDMULH, SQRDMULH to decodetree [v3,32/33] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree [v3,33/33] target/arm: Convert FCSEL to decodetree

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20240528203044.612851-26-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org,
	Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v3 25/33] target/arm: Convert SRHADD, URHADD to decodetree
Date: Tue, 28 May 2024 13:30:36 -0700
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Series

target/arm: Convert a64 advsimd to decodetree (part 1b) | expand

Commit Message

Richard Henderson May 28, 2024, 8:30 p.m. UTC

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/a64.decode      |  2 ++
 target/arm/tcg/translate-a64.c | 11 +++--------
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b1bbcb144e..1c448b4f7c 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -916,6 +916,8 @@  SHADD_v         0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
 UHADD_v         0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
 SHSUB_v         0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
 UHSUB_v         0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
+SRHADD_v        0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
+URHADD_v        0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
 
 ### Advanced SIMD scalar x indexed element
 
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 40aa7a9d57..9ef5de6755 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5458,6 +5458,8 @@  TRANS(SHADD_v, do_gvec_fn3_no64, a, gen_gvec_shadd)
 TRANS(UHADD_v, do_gvec_fn3_no64, a, gen_gvec_uhadd)
 TRANS(SHSUB_v, do_gvec_fn3_no64, a, gen_gvec_shsub)
 TRANS(UHSUB_v, do_gvec_fn3_no64, a, gen_gvec_uhsub)
+TRANS(SRHADD_v, do_gvec_fn3_no64, a, gen_gvec_srhadd)
+TRANS(URHADD_v, do_gvec_fn3_no64, a, gen_gvec_urhadd)
 
 static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
 {
@@ -10923,7 +10925,6 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
             return;
         }
         /* fall through */
-    case 0x2: /* SRHADD, URHADD */
     case 0xc: /* SMAX, UMAX */
     case 0xd: /* SMIN, UMIN */
     case 0xe: /* SABD, UABD */
@@ -10949,6 +10950,7 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
 
     case 0x0: /* SHADD, UHADD */
     case 0x01: /* SQADD, UQADD */
+    case 0x02: /* SRHADD, URHADD */
     case 0x04: /* SHSUB, UHSUB */
     case 0x05: /* SQSUB, UQSUB */
     case 0x06: /* CMGT, CMHI */
@@ -10968,13 +10970,6 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
     }
 
     switch (opcode) {
-    case 0x02: /* SRHADD, URHADD */
-        if (u) {
-            gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_urhadd, size);
-        } else {
-            gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_srhadd, size);
-        }
-        return;
     case 0x0c: /* SMAX, UMAX */
         if (u) {
             gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);

[v3,25/33] target/arm: Convert SRHADD, URHADD to decodetree

Commit Message

Patch