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[PULL,10/42] target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)

Message ID 20240528140753.3620597-11-peter.maydell@linaro.org
State Accepted
Commit fe84877ed44040dc128362b61dbfd923b851d6ef
Headers show
Series [PULL,01/42] xlnx_dpdma: fix descriptor endianness bug | expand

Commit Message

Peter Maydell May 28, 2024, 2:07 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

Fixes RISU mismatch for "fcvtzs h31, h0, #14".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-a64.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4126aaa27e6..d97acdbaf9a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8707,6 +8707,9 @@  static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
             read_vec_element_i32(s, tcg_op, rn, pass, size);
             fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
             if (is_scalar) {
+                if (size == MO_16 && !is_u) {
+                    tcg_gen_ext16u_i32(tcg_op, tcg_op);
+                }
                 write_fp_sreg(s, rd, tcg_op);
             } else {
                 write_vec_element_i32(s, tcg_op, rd, pass, size);