| Message ID | 20240528-topic-sm8x50-pinctrl-pinconf-v1-3-54d1e9ad7dfa@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: qcom: allow setting pins configuration for sepcial pins | expand |
On Tue, 28 May 2024 at 14:02, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > Use the previously introduced msm_special_pin_data to setup the special > pins configuration if the SoC driver have them specified. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/pinctrl/qcom/pinctrl-qcom.c | 37 +++++++++++++++++++++++++++++++++++-- > 1 file changed, 35 insertions(+), 2 deletions(-) > Reviewed-by: Sumit Garg <sumit.garg@linaro.org> -Sumit > diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c > index 4f4e9a83949..26a3fba194a 100644 > --- a/drivers/pinctrl/qcom/pinctrl-qcom.c > +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c > @@ -103,14 +103,47 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, > return 0; > } > > +static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector, > + unsigned int param, unsigned int argument) > +{ > + unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start; > + const struct msm_special_pin_data *data; > + > + if (!priv->data->pin_data.special_pins_data) > + return 0; > + > + data = &priv->data->pin_data.special_pins_data[offset]; > + > + switch (param) { > + case PIN_CONFIG_DRIVE_STRENGTH: > + argument = (argument / 2) - 1; > + clrsetbits_le32(priv->base + data->ctl_reg, > + GENMASK(2, 0) << data->drv_bit, > + argument << data->drv_bit); > + break; > + case PIN_CONFIG_BIAS_DISABLE: > + clrbits_le32(priv->base + data->ctl_reg, > + TLMM_GPIO_PULL_MASK << data->pull_bit); > + break; > + case PIN_CONFIG_BIAS_PULL_UP: > + clrsetbits_le32(priv->base + data->ctl_reg, > + TLMM_GPIO_PULL_MASK << data->pull_bit, > + argument << data->pull_bit); > + break; > + default: > + return 0; > + } > + > + return 0; > +} > + > static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, > unsigned int param, unsigned int argument) > { > struct msm_pinctrl_priv *priv = dev_get_priv(dev); > > - /* Always NOP for special pins */ > if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) > - return 0; > + return msm_pinconf_set_special(priv, pin_selector, param, argument); > > switch (param) { > case PIN_CONFIG_DRIVE_STRENGTH: > > -- > 2.34.1 >
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 4f4e9a83949..26a3fba194a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -103,14 +103,47 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; } +static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->data->pin_data.special_pins_data) + return 0; + + data = &priv->data->pin_data.special_pins_data[offset]; + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + argument = (argument / 2) - 1; + clrsetbits_le32(priv->base + data->ctl_reg, + GENMASK(2, 0) << data->drv_bit, + argument << data->drv_bit); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + data->ctl_reg, + TLMM_GPIO_PULL_MASK << data->pull_bit); + break; + case PIN_CONFIG_BIAS_PULL_UP: + clrsetbits_le32(priv->base + data->ctl_reg, + TLMM_GPIO_PULL_MASK << data->pull_bit, + argument << data->pull_bit); + break; + default: + return 0; + } + + return 0; +} + static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, unsigned int param, unsigned int argument) { struct msm_pinctrl_priv *priv = dev_get_priv(dev); - /* Always NOP for special pins */ if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) - return 0; + return msm_pinconf_set_special(priv, pin_selector, param, argument); switch (param) { case PIN_CONFIG_DRIVE_STRENGTH:
Use the previously introduced msm_special_pin_data to setup the special pins configuration if the SoC driver have them specified. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/pinctrl/qcom/pinctrl-qcom.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-)