[51/57] target/arm: Convert SRHADD, URHADD to decodetree

Message ID	20240506010403.6204-52-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 51/57] target/arm: Convert SRHADD, URHADD to decodetree Date: Sun, 5 May 2024 18:03:57 -0700 Message-Id: <20240506010403.6204-52-richard.henderson@linaro.org> In-Reply-To: <20240506010403.6204-1-richard.henderson@linaro.org> References: <20240506010403.6204-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Convert a64 advsimd to decodetree (part 1) \| expand [00/57] target/arm: Convert a64 advsimd to decodetree (part 1) [01/57] target/arm: Split out gengvec.c [02/57] target/arm: Split out gengvec64.c [03/57] target/arm: Convert Cryptographic AES to decodetree [04/57] target/arm: Convert Cryptographic 3-register SHA to decodetree [05/57] target/arm: Convert Cryptographic 2-register SHA to decodetree [06/57] target/arm: Convert Cryptographic 3-register SHA512 to decodetree [07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree [08/57] target/arm: Convert Cryptographic 4-register to decodetree [09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree [10/57] target/arm: Convert XAR to decodetree [11/57] target/arm: Convert Advanced SIMD copy to decodetree [12/57] target/arm: Convert FMULX to decodetree [13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree [14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree [15/57] target/arm: Expand vfp neg and abs inline [16/57] target/arm: Convert FNMUL to decodetree [17/57] target/arm: Convert FMLA, FMLS to decodetree [18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree [19/57] target/arm: Convert FABD to decodetree [20/57] target/arm: Convert FRECPS, FRSQRTS to decodetree [21/57] target/arm: Convert FADDP to decodetree [22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree [23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp [24/57] target/arm: Convert ADDP to decodetree [25/57] target/arm: Use gvec for neon padd [26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree [27/57] target/arm: Use gvec for neon pmax, pmin [28/57] target/arm: Convert FMLAL, FMLSL to decodetree [29/57] target/arm: Convert disas_simd_3same_logic to decodetree [30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB [31/57] target/arm: Convert SUQADD and USQADD to gvec [32/57] target/arm: Inline scalar SUQADD and USQADD [33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB [34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree [35/57] target/arm: Convert SUQADD, USQADD to decodetree [36/57] target/arm: Convert SSHL, USHL to decodetree [37/57] target/arm: Convert SRSHL and URSHL (register) to gvec [38/57] target/arm: Convert SRSHL, URSHL to decodetree [39/57] target/arm: Convert SQSHL and UQSHL (register) to gvec [40/57] target/arm: Convert SQSHL, UQSHL to decodetree [41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec [42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree [43/57] target/arm: Convert ADD, SUB (vector) to decodetree [44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree [45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64} [46/57] target/arm: Convert SHADD, UHADD to gvec [47/57] target/arm: Convert SHADD, UHADD to decodetree [48/57] target/arm: Convert SHSUB, UHSUB to gvec [49/57] target/arm: Convert SHSUB, UHSUB to decodetree [50/57] target/arm: Convert SRHADD, URHADD to gvec [51/57] target/arm: Convert SRHADD, URHADD to decodetree [52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree [53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree [54/57] target/arm: Convert MUL, PMUL to decodetree [55/57] target/arm: Convert MLA, MLS to decodetree [56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector) [57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

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20240506010403.6204-52-richard.henderson@linaro.org

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Cc: qemu-arm@nongnu.org
Subject: [PATCH 51/57] target/arm: Convert SRHADD, URHADD to decodetree
Date: Sun,  5 May 2024 18:03:57 -0700
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Series

target/arm: Convert a64 advsimd to decodetree (part 1) | expand

Commit Message

Richard Henderson May 6, 2024, 1:03 a.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/a64.decode      |  2 ++
 target/arm/tcg/translate-a64.c | 11 +++--------
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 80c4c650c9..fc8a5ca14f 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -916,6 +916,8 @@  SHADD_v         0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
 UHADD_v         0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
 SHSUB_v         0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
 UHSUB_v         0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
+SRHADD_v        0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
+URHADD_v        0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
 
 ### Advanced SIMD scalar x indexed element
 
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 87b86b7c54..b707c6ae4d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5459,6 +5459,8 @@  TRANS(SHADD_v, do_gvec_fn3_no64, a, gen_gvec_shadd)
 TRANS(UHADD_v, do_gvec_fn3_no64, a, gen_gvec_uhadd)
 TRANS(SHSUB_v, do_gvec_fn3_no64, a, gen_gvec_shsub)
 TRANS(UHSUB_v, do_gvec_fn3_no64, a, gen_gvec_uhsub)
+TRANS(SRHADD_v, do_gvec_fn3_no64, a, gen_gvec_srhadd)
+TRANS(URHADD_v, do_gvec_fn3_no64, a, gen_gvec_urhadd)
 
 static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
 {
@@ -10917,7 +10919,6 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
             return;
         }
         /* fall through */
-    case 0x2: /* SRHADD, URHADD */
     case 0xc: /* SMAX, UMAX */
     case 0xd: /* SMIN, UMIN */
     case 0xe: /* SABD, UABD */
@@ -10943,6 +10944,7 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
 
     case 0x0: /* SHADD, UHADD */
     case 0x01: /* SQADD, UQADD */
+    case 0x02: /* SRHADD, URHADD */
     case 0x04: /* SHSUB, UHSUB */
     case 0x05: /* SQSUB, UQSUB */
     case 0x06: /* CMGT, CMHI */
@@ -10962,13 +10964,6 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
     }
 
     switch (opcode) {
-    case 0x02: /* SRHADD, URHADD */
-        if (u) {
-            gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_urhadd, size);
-        } else {
-            gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_srhadd, size);
-        }
-        return;
     case 0x0c: /* SMAX, UMAX */
         if (u) {
             gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);

[51/57] target/arm: Convert SRHADD, URHADD to decodetree

Commit Message

Patch