[25/57] target/arm: Use gvec for neon padd

Message ID	20240506010403.6204-26-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 25/57] target/arm: Use gvec for neon padd Date: Sun, 5 May 2024 18:03:31 -0700 Message-Id: <20240506010403.6204-26-richard.henderson@linaro.org> In-Reply-To: <20240506010403.6204-1-richard.henderson@linaro.org> References: <20240506010403.6204-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Convert a64 advsimd to decodetree (part 1) \| expand [00/57] target/arm: Convert a64 advsimd to decodetree (part 1) [01/57] target/arm: Split out gengvec.c [02/57] target/arm: Split out gengvec64.c [03/57] target/arm: Convert Cryptographic AES to decodetree [04/57] target/arm: Convert Cryptographic 3-register SHA to decodetree [05/57] target/arm: Convert Cryptographic 2-register SHA to decodetree [06/57] target/arm: Convert Cryptographic 3-register SHA512 to decodetree [07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree [08/57] target/arm: Convert Cryptographic 4-register to decodetree [09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree [10/57] target/arm: Convert XAR to decodetree [11/57] target/arm: Convert Advanced SIMD copy to decodetree [12/57] target/arm: Convert FMULX to decodetree [13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree [14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree [15/57] target/arm: Expand vfp neg and abs inline [16/57] target/arm: Convert FNMUL to decodetree [17/57] target/arm: Convert FMLA, FMLS to decodetree [18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree [19/57] target/arm: Convert FABD to decodetree [20/57] target/arm: Convert FRECPS, FRSQRTS to decodetree [21/57] target/arm: Convert FADDP to decodetree [22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree [23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp [24/57] target/arm: Convert ADDP to decodetree [25/57] target/arm: Use gvec for neon padd [26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree [27/57] target/arm: Use gvec for neon pmax, pmin [28/57] target/arm: Convert FMLAL, FMLSL to decodetree [29/57] target/arm: Convert disas_simd_3same_logic to decodetree [30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB [31/57] target/arm: Convert SUQADD and USQADD to gvec [32/57] target/arm: Inline scalar SUQADD and USQADD [33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB [34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree [35/57] target/arm: Convert SUQADD, USQADD to decodetree [36/57] target/arm: Convert SSHL, USHL to decodetree [37/57] target/arm: Convert SRSHL and URSHL (register) to gvec [38/57] target/arm: Convert SRSHL, URSHL to decodetree [39/57] target/arm: Convert SQSHL and UQSHL (register) to gvec [40/57] target/arm: Convert SQSHL, UQSHL to decodetree [41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec [42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree [43/57] target/arm: Convert ADD, SUB (vector) to decodetree [44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree [45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64} [46/57] target/arm: Convert SHADD, UHADD to gvec [47/57] target/arm: Convert SHADD, UHADD to decodetree [48/57] target/arm: Convert SHSUB, UHSUB to gvec [49/57] target/arm: Convert SHSUB, UHSUB to decodetree [50/57] target/arm: Convert SRHADD, URHADD to gvec [51/57] target/arm: Convert SRHADD, URHADD to decodetree [52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree [53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree [54/57] target/arm: Convert MUL, PMUL to decodetree [55/57] target/arm: Convert MLA, MLS to decodetree [56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector) [57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree

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20240506010403.6204-26-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 25/57] target/arm: Use gvec for neon padd
Date: Sun,  5 May 2024 18:03:31 -0700
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Series

target/arm: Convert a64 advsimd to decodetree (part 1) | expand

Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.h | 2 -- target/arm/tcg/neon_helper.c | 5 ----- target/arm/tcg/translate-neon.c | 3 +-- 3 files changed, 1 insertion(+), 9 deletions(-)

Comments

Peter Maydell May 23, 2024, 1:59 p.m. UTC | #1

On Mon, 6 May 2024 at 02:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

diff --git a/target/arm/helper.h b/target/arm/helper.h
index d3579a101f..51ed49aa50 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -354,8 +354,6 @@  DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
 
 DEF_HELPER_2(neon_add_u8, i32, i32, i32)
 DEF_HELPER_2(neon_add_u16, i32, i32, i32)
-DEF_HELPER_2(neon_padd_u8, i32, i32, i32)
-DEF_HELPER_2(neon_padd_u16, i32, i32, i32)
 DEF_HELPER_2(neon_sub_u8, i32, i32, i32)
 DEF_HELPER_2(neon_sub_u16, i32, i32, i32)
 DEF_HELPER_2(neon_mul_u8, i32, i32, i32)
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index bc6c4a54e9..a0b51c8809 100644
--- a/target/arm/tcg/neon_helper.c
+++ b/target/arm/tcg/neon_helper.c
@@ -745,11 +745,6 @@  uint32_t HELPER(neon_add_u16)(uint32_t a, uint32_t b)
     return (a + b) ^ mask;
 }
 
-#define NEON_FN(dest, src1, src2) dest = src1 + src2
-NEON_POP(padd_u8, neon_u8, 4)
-NEON_POP(padd_u16, neon_u16, 2)
-#undef NEON_FN
-
 #define NEON_FN(dest, src1, src2) dest = src1 - src2
 NEON_VOP(sub_u8, neon_u8, 4)
 NEON_VOP(sub_u16, neon_u16, 2)
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 2326a05a0a..6c5a7a98e1 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -830,6 +830,7 @@  DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd)
 DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba)
 DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd)
 DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba)
+DO_3SAME_NO_SZ_3(VPADD, gen_gvec_addp)
 
 #define DO_3SAME_CMP(INSN, COND)                                        \
     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
@@ -1070,13 +1071,11 @@  static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
 #define gen_helper_neon_pmax_u32  tcg_gen_umax_i32
 #define gen_helper_neon_pmin_s32  tcg_gen_smin_i32
 #define gen_helper_neon_pmin_u32  tcg_gen_umin_i32
-#define gen_helper_neon_padd_u32  tcg_gen_add_i32
 
 DO_3SAME_PAIR(VPMAX_S, pmax_s)
 DO_3SAME_PAIR(VPMIN_S, pmin_s)
 DO_3SAME_PAIR(VPMAX_U, pmax_u)
 DO_3SAME_PAIR(VPMIN_U, pmin_u)
-DO_3SAME_PAIR(VPADD, padd_u)
 
 #define DO_3SAME_VQDMULH(INSN, FUNC)                                    \
     WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16);    \

[25/57] target/arm: Use gvec for neon padd

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