@@ -28,25 +28,22 @@
static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
-
- cpu->env.pc = value;
+ CPUAlphaState *env = cpu_env(cs);
+ env->pc = value;
}
static vaddr alpha_cpu_get_pc(CPUState *cs)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
-
- return cpu->env.pc;
+ CPUAlphaState *env = cpu_env(cs);
+ return env->pc;
}
static void alpha_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
-
- cpu->env.pc = data[0];
+ CPUAlphaState *env = cpu_env(cs);
+ env->pc = data[0];
}
static bool alpha_cpu_has_work(CPUState *cs)
@@ -124,7 +124,7 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
MMUAccessType access_type,
bool maperr, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = cpu_env(cs);
target_ulong mmcsr, cause;
/* Assuming !maperr, infer the missing protection. */
@@ -155,9 +155,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
}
/* Record the arguments that PALcode would give to the kernel. */
- cpu->env.trap_arg0 = address;
- cpu->env.trap_arg1 = mmcsr;
- cpu->env.trap_arg2 = cause;
+ env->trap_arg0 = address;
+ env->trap_arg1 = mmcsr;
+ env->trap_arg2 = cause;
}
#else
/* Returns the OSF/1 entMM failure indication, or -1 on success. */