[v8,01/24] RISC-V: Fix the typo in Scountovf CSR name

Message ID	20240420151741.962500-2-atishp@rivosinc.com
State	Accepted
Commit	d1927f64e0e1094f296842e127138cb5f3bf3c6d
Headers	show Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1216513D899 for <linux-kselftest@vger.kernel.org>; Fri, 19 Apr 2024 23:47:46 +0000 (UTC) From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Andrew Jones <ajones@ventanamicro.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, samuel.holland@sifive.com, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v8 01/24] RISC-V: Fix the typo in Scountovf CSR name Date: Sat, 20 Apr 2024 08:17:17 -0700 Message-Id: <20240420151741.962500-2-atishp@rivosinc.com> In-Reply-To: <20240420151741.962500-1-atishp@rivosinc.com> References: <20240420151741.962500-1-atishp@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v8,00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v8,01/24] RISC-V: Fix the typo in Scountovf CSR name [v8,02/24] RISC-V: Add FIRMWARE_READ_HI definition [v8,03/24] drivers/perf: riscv: Read upper bits of a firmware counter [v8,04/24] drivers/perf: riscv: Use BIT macro for shifting operations [v8,05/24] RISC-V: Add SBI PMU snapshot definitions [v8,06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name [v8,07/24] RISC-V: Use the minor version mask while computing sbi version [v8,08/24] drivers/perf: riscv: Fix counter mask iteration for RV32 [v8,09/24] drivers/perf: riscv: Implement SBI PMU snapshot function [v8,10/24] RISC-V: KVM: Fix the initial sample period value [v8,11/24] RISC-V: KVM: No need to update the counter value during reset [v8,12/24] RISC-V: KVM: No need to exit to the user space if perf event failed [v8,13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature [v8,14/24] RISC-V: KVM: Add perf sampling support for guests [v8,15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 [v8,16/24] RISC-V: KVM: Improve firmware counter read function [v8,17/24] KVM: riscv: selftests: Move sbi definitions to its own header file [v8,18/24] KVM: riscv: selftests: Add helper functions for extension checks [v8,19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test [v8,20/24] KVM: riscv: selftests: Add SBI PMU extension definitions [v8,21/24] KVM: riscv: selftests: Add SBI PMU selftest [v8,22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality [v8,23/24] KVM: riscv: selftests: Add a test for counter overflow [v8,24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

Message ID

20240420151741.962500-2-atishp@rivosinc.com

State

Accepted

Commit

d1927f64e0e1094f296842e127138cb5f3bf3c6d

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
 =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
 Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>,
 Andrew Jones <ajones@ventanamicro.com>, Ajay Kaher <ajay.kaher@broadcom.com>,
 Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>,
 samuel.holland@sifive.com, Juergen Gross <jgross@suse.com>,
 kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
 linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
 Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>,
 Paolo Bonzini <pbonzini@redhat.com>,
 Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>,
 virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org
Subject: [PATCH v8 01/24] RISC-V: Fix the typo in Scountovf CSR name
Date: Sat, 20 Apr 2024 08:17:17 -0700
Message-Id: <20240420151741.962500-2-atishp@rivosinc.com>
In-Reply-To: <20240420151741.962500-1-atishp@rivosinc.com>
References: <20240420151741.962500-1-atishp@rivosinc.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Kumar Patra April 20, 2024, 3:17 p.m. UTC

The counter overflow CSR name is "scountovf" not "sscountovf".

Fix the csr name.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 2 +-
 drivers/perf/riscv_pmu_sbi.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..9d1b07932794 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -281,7 +281,7 @@ 
 #define CSR_HPMCOUNTER30H	0xc9e
 #define CSR_HPMCOUNTER31H	0xc9f
 
-#define CSR_SSCOUNTOVF		0xda0
+#define CSR_SCOUNTOVF		0xda0
 
 #define CSR_SSTATUS		0x100
 #define CSR_SIE			0x104
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 8cbe6e5f9c39..3e44d2fb8bf8 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -27,7 +27,7 @@ 
 
 #define ALT_SBI_PMU_OVERFLOW(__ovl)					\
 asm volatile(ALTERNATIVE_2(						\
-	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\
+	"csrr %0, " __stringify(CSR_SCOUNTOVF),				\
 	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\
 		THEAD_VENDOR_ID, ERRATA_THEAD_PMU,			\
 		CONFIG_ERRATA_THEAD_PMU,				\

[v8,01/24] RISC-V: Fix the typo in Scountovf CSR name

Commit Message

Patch