diff mbox series

[PATCH-for-9.1,v2,05/11] hw/net/lan9118: Add definitions for FIFO allocated sizes

Message ID 20240409133801.23503-6-philmd@linaro.org
State New
Headers show
Series hw/net/lan9118: Fix overflow in TX FIFO | expand

Commit Message

Philippe Mathieu-Daudé April 9, 2024, 1:37 p.m. UTC 
Add definitions for the TX_FIF_SZ=5 case, per TABLE 5-3
"VALID TX/RX FIFO ALLOCATIONS".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/net/lan9118.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Peter Maydell April 9, 2024, 1:52 p.m. UTC | #1 
On Tue, 9 Apr 2024 at 14:39, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Add definitions for the TX_FIF_SZ=5 case, per TABLE 5-3
> "VALID TX/RX FIFO ALLOCATIONS".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  hw/net/lan9118.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
> index a6a869de32..00409927fe 100644
> --- a/hw/net/lan9118.c
> +++ b/hw/net/lan9118.c
> @@ -158,6 +158,17 @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
>   */
>  #define MIL_TXFIFO_SIZE         2048
>
> +/*
> + * TX and RX FIFO space is configurable through the TX FIFO Size (TX_FIF_SZ)
> + * field in the hardware configuration (CSR HW_CFG) register. These are the
> + * default configuration settings for TX_FIF_SZ = 5
> + * (see TABLE 5-3: VALID TX/RX FIFO ALLOCATIONS).
> + */
> +#define TX_DATA_FIFO_BYTES      4608    /* 1152 words */
> +#define TX_STATUS_FIFO_BYTES    512     /* 128 words */
> +#define RX_DATA_FIFO_BYTES      10560   /* 2640 words */
> +#define RX_STATUS_FIFO_BYTES    704     /* 176 words */

We could make these do the actual calculations, rather
than hardcoding the results:

#define TX_STATUS_FIFO_BYTES 512
#define TX_TOTAL_FIFO_BYTES(TX_FIF_SZ) (1024 * (TX_FIF_SZ))
#define RX_TOTAL_FIFO_BYTES(TX_FIF_SZ) (16384 - TX_TOTAL_FIFO_BYTES(TX_FIF_SZ))
#define TX_DATA_FIFO_BYTES(TX_FIF_SZ) (TX_TOTAL_FIFO_BYTES(TX_FIF_SZ)
- TX_STATUS_FIFO_BYTES)
#define RX_STATUS_FIFO_BYTES (RX_TOTAL_FIFO_BYTES(TX_FIF_SZ) >> 4)
#define RX_DATA_FIFO_BYTES(TX_FIF_SZ) \
    (RX_TOTAL_FIFO_BYTES(TX_FIF_SZ) - RX_STATUS_FIFO_BYTES(TX_FIF_SZ))

thanks
-- PMM
diff mbox series

Patch

diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index a6a869de32..00409927fe 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -158,6 +158,17 @@  do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
  */
 #define MIL_TXFIFO_SIZE         2048
 
+/*
+ * TX and RX FIFO space is configurable through the TX FIFO Size (TX_FIF_SZ)
+ * field in the hardware configuration (CSR HW_CFG) register. These are the
+ * default configuration settings for TX_FIF_SZ = 5
+ * (see TABLE 5-3: VALID TX/RX FIFO ALLOCATIONS).
+ */
+#define TX_DATA_FIFO_BYTES      4608    /* 1152 words */
+#define TX_STATUS_FIFO_BYTES    512     /* 128 words */
+#define RX_DATA_FIFO_BYTES      10560   /* 2640 words */
+#define RX_STATUS_FIFO_BYTES    704     /* 176 words */
+
 enum tx_state {
     TX_IDLE,
     TX_B,