@@ -242,7 +242,7 @@ static struct qcom_icc_node crypto_c0 = {
.id = SM6115_MASTER_CRYPTO_CORE0,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 43,
+ .qos.qos_port = 22,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = 23,
@@ -332,7 +332,7 @@ static struct qcom_icc_node qnm_camera_nrt = {
.id = SM6115_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
- .qos.qos_port = 25,
+ .qos.qos_port = 4,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 3,
.mas_rpm_id = -1,
@@ -346,7 +346,7 @@ static struct qcom_icc_node qxm_venus0 = {
.id = SM6115_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 16,
- .qos.qos_port = 30,
+ .qos.qos_port = 9,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 3,
.qos.urg_fwd_en = true,
@@ -361,7 +361,7 @@ static struct qcom_icc_node qxm_venus_cpu = {
.id = SM6115_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 34,
+ .qos.qos_port = 13,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 4,
.mas_rpm_id = -1,
@@ -379,7 +379,7 @@ static struct qcom_icc_node qnm_camera_rt = {
.id = SM6115_MASTER_CAMNOC_HF,
.channels = 1,
.buswidth = 32,
- .qos.qos_port = 31,
+ .qos.qos_port = 10,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 3,
.qos.urg_fwd_en = true,
@@ -394,7 +394,7 @@ static struct qcom_icc_node qxm_mdp0 = {
.id = SM6115_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 16,
- .qos.qos_port = 26,
+ .qos.qos_port = 5,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 3,
.qos.urg_fwd_en = true,
@@ -434,7 +434,7 @@ static struct qcom_icc_node qhm_tic = {
.id = SM6115_MASTER_TIC,
.channels = 1,
.buswidth = 4,
- .qos.qos_port = 29,
+ .qos.qos_port = 8,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = -1,
@@ -484,7 +484,7 @@ static struct qcom_icc_node qxm_pimem = {
.id = SM6115_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 41,
+ .qos.qos_port = 20,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = -1,
@@ -498,7 +498,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.id = SM6115_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .qos.qos_port = 23,
+ .qos.qos_port = 2,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = -1,
@@ -523,7 +523,7 @@ static struct qcom_icc_node qhm_qup0 = {
.id = SM6115_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
- .qos.qos_port = 21,
+ .qos.qos_port = 0,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = 166,
@@ -537,7 +537,7 @@ static struct qcom_icc_node qxm_ipa = {
.id = SM6115_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 24,
+ .qos.qos_port = 3,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = 59,
@@ -551,7 +551,7 @@ static struct qcom_icc_node xm_qdss_etr = {
.id = SM6115_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 33,
+ .qos.qos_port = 12,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = -1,
@@ -565,7 +565,7 @@ static struct qcom_icc_node xm_sdc1 = {
.id = SM6115_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 38,
+ .qos.qos_port = 17,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = 33,
@@ -579,7 +579,7 @@ static struct qcom_icc_node xm_sdc2 = {
.id = SM6115_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 44,
+ .qos.qos_port = 23,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = 35,
@@ -593,7 +593,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.id = SM6115_MASTER_USB3,
.channels = 1,
.buswidth = 8,
- .qos.qos_port = 45,
+ .qos.qos_port = 24,
.qos.qos_mode = NOC_QOS_MODE_FIXED,
.qos.areq_prio = 2,
.mas_rpm_id = -1,
@@ -1336,6 +1336,7 @@ static const struct qcom_icc_desc sm6115_sys_noc = {
.intf_clocks = snoc_intf_clocks,
.num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks),
.bus_clk_desc = &bus_2_clk,
+ .qos_offset = 0x15000,
.keep_alive = true,
};
@@ -1367,6 +1368,7 @@ static const struct qcom_icc_desc sm6115_mmnrt_virt = {
.regmap_cfg = &sys_noc_regmap_config,
.bus_clk_desc = &mmaxi_0_clk,
.keep_alive = true,
+ .qos_offset = 0x15000,
.ab_coeff = 142,
};
@@ -1383,6 +1385,7 @@ static const struct qcom_icc_desc sm6115_mmrt_virt = {
.regmap_cfg = &sys_noc_regmap_config,
.bus_clk_desc = &mmaxi_1_clk,
.keep_alive = true,
+ .qos_offset = 0x15000,
.ab_coeff = 139,
};
When I was creating this driver, my bright mind overlooked the existence of desc->qos_offset and decided to make up for the difference it made by adding 21 (0x15) to the port index on SNoC and its downstream buses. Undo this mistake to make the indices actually mean something. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/interconnect/qcom/sm6115.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-)