| Message ID | 20240219-topic-rb1_gpu-v3-2-86f67786539a@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | A702 support | expand |
Quoting Konrad Dybcio (2024-03-26 14:08:24) > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 8a412ef47e16..27ba8aa3e577 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -779,6 +792,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, > return clamp(rate, min_freq, max_freq); > } > > +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > + const struct alpha_pll_config *config) > +{ > + u32 val; > + > + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); > + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); > + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); > + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); > + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); > + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); > + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); > + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); > + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); > + > + /* Set PLL_BYPASSNL */ > + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); > + regmap_read(regmap, PLL_MODE(pll), &val); > + > + /* Wait 5 us between setting BYPASS and deasserting reset */ > + udelay(5); > + > + /* Take PLL out from reset state */ > + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); > + regmap_read(regmap, PLL_MODE(pll), &val); > + > + /* Wait 50us for PLL_LOCK_DET bit to go high */ Is the bit not reliable or something? I'd expect to see a polling loop here but it's a sleep. > + usleep_range(50, 55);
On 5.04.2024 11:37 PM, Stephen Boyd wrote: > Quoting Konrad Dybcio (2024-03-26 14:08:24) >> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c >> index 8a412ef47e16..27ba8aa3e577 100644 >> --- a/drivers/clk/qcom/clk-alpha-pll.c >> +++ b/drivers/clk/qcom/clk-alpha-pll.c >> @@ -779,6 +792,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, >> return clamp(rate, min_freq, max_freq); >> } >> >> +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> + const struct alpha_pll_config *config) >> +{ >> + u32 val; >> + >> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); >> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); >> + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); >> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); >> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); >> + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); >> + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); >> + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); >> + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); >> + >> + /* Set PLL_BYPASSNL */ >> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); >> + regmap_read(regmap, PLL_MODE(pll), &val); >> + >> + /* Wait 5 us between setting BYPASS and deasserting reset */ >> + udelay(5); >> + >> + /* Take PLL out from reset state */ >> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); >> + regmap_read(regmap, PLL_MODE(pll), &val); >> + >> + /* Wait 50us for PLL_LOCK_DET bit to go high */ > > Is the bit not reliable or something? I'd expect to see a polling loop > here but it's a sleep. Unfortunately, it seems so. Konrad
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 8a412ef47e16..27ba8aa3e577 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -83,6 +83,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x20, [PLL_OFF_STATUS] = 0x24, }, + [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL_U1] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_TEST_CTL_U1] = 0x24, + [PLL_OFF_OPMODE] = 0x28, + [PLL_OFF_STATUS] = 0x38, + }, [CLK_ALPHA_PLL_TYPE_BRAMMO] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -779,6 +792,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 val; + + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + + /* Set PLL_BYPASSNL */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 5 us between setting BYPASS and deasserting reset */ + udelay(5); + + /* Take PLL out from reset state */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 50us for PLL_LOCK_DET bit to go high */ + usleep_range(50, 55); + + /* Enable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} +EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); + static unsigned long alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index fb6d50263bb9..d1cd52158c17 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -15,6 +15,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT, CLK_ALPHA_PLL_TYPE_HUAYRA, + CLK_ALPHA_PLL_TYPE_HUAYRA_2290, CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_FABIA, CLK_ALPHA_PLL_TYPE_TRION, @@ -191,6 +192,8 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/clk/qcom/clk-alpha-pll.c | 47 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 50 insertions(+)