| Message ID | 20240318212428.3843952-8-nico@fluxnic.net |
|---|---|
| State | New |
| Headers | show |
| Series | Mediatek thermal sensor driver support for MT8186 and MT8188 | expand |
Il 18/03/24 22:22, Nicolas Pitre ha scritto: > From: Nicolas Pitre <npitre@baylibre.com> > > Various values extracted from the vendor's kernel driver. > > Signed-off-by: Nicolas Pitre <npitre@baylibre.com> > --- > drivers/thermal/mediatek/lvts_thermal.c | 67 +++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c > index ed1888fb24..e923d22c17 100644 > --- a/drivers/thermal/mediatek/lvts_thermal.c > +++ b/drivers/thermal/mediatek/lvts_thermal.c > @@ -80,6 +80,8 @@ > #define LVTS_SENSOR_MAX 4 > #define LVTS_GOLDEN_TEMP_MAX 62 > #define LVTS_GOLDEN_TEMP_DEFAULT 50 > +#define LVTS_COEFF_A_MT8186 -204650 > +#define LVTS_COEFF_B_MT8186 204650 You don't need this definition, as you can reuse the MT7988 one. Regards, Angelo > #define LVTS_COEFF_A_MT8195 -250460 > #define LVTS_COEFF_B_MT8195 250460 > #define LVTS_COEFF_A_MT7988 -204650 > @@ -92,6 +94,7 @@ > #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) > > #define LVTS_HW_SHUTDOWN_MT7988 105000 > +#define LVTS_HW_SHUTDOWN_MT8186 105000 > #define LVTS_HW_SHUTDOWN_MT8192 105000 > #define LVTS_HW_SHUTDOWN_MT8195 105000 > > @@ -1377,6 +1380,62 @@ static int lvts_resume(struct device *dev) > return 0; > } > > +/* > + * The MT8186 calibration data is stored as packed 3-byte little-endian > + * values using a weird layout that makes sense only when viewed as a 32-bit > + * hexadecimal word dump. Let's suppose SxBy where x = sensor number and > + * y = byte number where the LSB is y=0. We then have: > + * > + * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] > + * > + * However, when considering a byte stream, those appear as follows: > + * > + * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] > + * > + * Hence the rather confusing offsets provided below. > + */ > +static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { > + { > + .lvts_sensor = { > + { .dt_id = MT8186_TS1_0, > + .cal_offsets = { 5, 6, 7 } }, > + { .dt_id = MT8186_TS1_1, > + .cal_offsets = { 10, 11, 4 } }, > + { .dt_id = MT8186_TS1_2, > + .cal_offsets = { 15, 8, 9 } }, > + { .dt_id = MT8186_TS1_3, > + .cal_offsets = { 12, 13, 14 } } > + }, > + .num_lvts_sensor = 4, > + .offset = 0x0, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, > + }, > + { > + .lvts_sensor = { > + { .dt_id = MT8186_TS2_0, > + .cal_offsets = { 22, 23, 16 } }, > + { .dt_id = MT8186_TS2_1, > + .cal_offsets = { 27, 20, 21 } } > + }, > + .num_lvts_sensor = 2, > + .offset = 0x100, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, > + }, > + { > + .lvts_sensor = { > + { .dt_id = MT8186_TS3_0, > + .cal_offsets = { 29, 30, 31 } }, > + { .dt_id = MT8186_TS3_1, > + .cal_offsets = { 34, 35, 28 } }, > + { .dt_id = MT8186_TS3_2, > + .cal_offsets = { 39, 32, 33 } } > + }, > + .num_lvts_sensor = 3, > + .offset = 0x200, > + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, > + } > +}; > + > static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { > { > .lvts_sensor = { > @@ -1565,6 +1624,13 @@ static const struct lvts_data mt7988_lvts_ap_data = { > .temp_offset = LVTS_COEFF_B_MT7988, > }; > > +static const struct lvts_data mt8186_lvts_data = { > + .lvts_ctrl = mt8186_lvts_data_ctrl, > + .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), > + .temp_factor = LVTS_COEFF_A_MT8186, > + .temp_offset = LVTS_COEFF_B_MT8186, > +}; > + > static const struct lvts_data mt8192_lvts_mcu_data = { > .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, > .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), > @@ -1591,6 +1657,7 @@ static const struct lvts_data mt8195_lvts_ap_data = { > > static const struct of_device_id lvts_of_match[] = { > { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, > + { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, > { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, > { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, > { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index ed1888fb24..e923d22c17 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -80,6 +80,8 @@ #define LVTS_SENSOR_MAX 4 #define LVTS_GOLDEN_TEMP_MAX 62 #define LVTS_GOLDEN_TEMP_DEFAULT 50 +#define LVTS_COEFF_A_MT8186 -204650 +#define LVTS_COEFF_B_MT8186 204650 #define LVTS_COEFF_A_MT8195 -250460 #define LVTS_COEFF_B_MT8195 250460 #define LVTS_COEFF_A_MT7988 -204650 @@ -92,6 +94,7 @@ #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) #define LVTS_HW_SHUTDOWN_MT7988 105000 +#define LVTS_HW_SHUTDOWN_MT8186 105000 #define LVTS_HW_SHUTDOWN_MT8192 105000 #define LVTS_HW_SHUTDOWN_MT8195 105000 @@ -1377,6 +1380,62 @@ static int lvts_resume(struct device *dev) return 0; } +/* + * The MT8186 calibration data is stored as packed 3-byte little-endian + * values using a weird layout that makes sense only when viewed as a 32-bit + * hexadecimal word dump. Let's suppose SxBy where x = sensor number and + * y = byte number where the LSB is y=0. We then have: + * + * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] + * + * However, when considering a byte stream, those appear as follows: + * + * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] + * + * Hence the rather confusing offsets provided below. + */ +static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { + { + .lvts_sensor = { + { .dt_id = MT8186_TS1_0, + .cal_offsets = { 5, 6, 7 } }, + { .dt_id = MT8186_TS1_1, + .cal_offsets = { 10, 11, 4 } }, + { .dt_id = MT8186_TS1_2, + .cal_offsets = { 15, 8, 9 } }, + { .dt_id = MT8186_TS1_3, + .cal_offsets = { 12, 13, 14 } } + }, + .num_lvts_sensor = 4, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, + }, + { + .lvts_sensor = { + { .dt_id = MT8186_TS2_0, + .cal_offsets = { 22, 23, 16 } }, + { .dt_id = MT8186_TS2_1, + .cal_offsets = { 27, 20, 21 } } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, + }, + { + .lvts_sensor = { + { .dt_id = MT8186_TS3_0, + .cal_offsets = { 29, 30, 31 } }, + { .dt_id = MT8186_TS3_1, + .cal_offsets = { 34, 35, 28 } }, + { .dt_id = MT8186_TS3_2, + .cal_offsets = { 39, 32, 33 } } + }, + .num_lvts_sensor = 3, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8186, + } +}; + static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { { .lvts_sensor = { @@ -1565,6 +1624,13 @@ static const struct lvts_data mt7988_lvts_ap_data = { .temp_offset = LVTS_COEFF_B_MT7988, }; +static const struct lvts_data mt8186_lvts_data = { + .lvts_ctrl = mt8186_lvts_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), + .temp_factor = LVTS_COEFF_A_MT8186, + .temp_offset = LVTS_COEFF_B_MT8186, +}; + static const struct lvts_data mt8192_lvts_mcu_data = { .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), @@ -1591,6 +1657,7 @@ static const struct lvts_data mt8195_lvts_ap_data = { static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, + { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },