| Message ID | 1476796207-94336-15-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On Tue, Oct 18, 2016 at 09:09:58PM +0800, Heyi Guo wrote: > phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the > typo. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > --- > Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > index f424ae9..8968b21 100644 > --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h > +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ > UINT8 per_cs_training_en; > UINT32 phyRdDataEnIeDly; > UINT32 phyPadCalConfig; > - UINT32 phyDqsFailRiseDelay; > + UINT32 phyDqsFallRiseDelay; > UINT32 ddrcCfgDfiLat0; > UINT32 ddrcCfgDfiLat1; > UINT32 parityLatency; The patch on its own is good, but while grepping through the tree I spotted this present as a string in: Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi matches Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi matches I believe these are debug strings in said components. Could you also provide updated versions of these with the strings fixed, to reduce debug confusion? Regards, Leif > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..8968b21 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;
phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)